顶层模块
module Top_Level(
clk,
rst_n,
ddr,
data
);
input clk;
input rst_n;
output [7:0]data;
output [5:0]ddr;
wire clk_10k;
wire pll_rst;
//assign pll_rst = ~rst_n;
PLL U0(
.inclk0(clk),
.c0(clk_10k),
.areset(!rst_n)
);
//assign clk_10k = clk
wire [3:0] bit_1;
wire [3:0] bit_2;
wire [3:0] bit_3;
wire [3:0] bit_4;
wire [3:0] bit_5;
wire [3:0] bit_6;
wire [19:0]indata = 20'd123456;
mod U1(
.CLK(clk_10k),
.RST_n(rst_n),
.IN_DATA(indata),
.bit_1(bit_1),
.bit_2(bit_2),
.bit_3(bit_3),
.bit_4(bit_4),
.bit_5(bit_5),
.bit_6(bit_6)
);
decoder U2(
.CLK(clk_10k),
.RST_n(rst_n),
.BIT_1(bit_1),
.BIT_2(bit_2),
.BIT_3(bit_3),
.BIT_4(bit_4),
.BIT_5(bit_5),
.BIT_6(bit_6),
.DATA_DDR(ddr),
.DATA_BUS(data)
);
endmodule
、
硬件能跑 仿真时钟输出抽风
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