[FPGA] 如何用FPGA实现CAN控制器

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 楼主| syt6702 发表于 2017-3-31 11:05 | 显示全部楼层 |阅读模式
我正在做一个项目需要用到FPAG并且需要在上面实现CAN通信控制器,请问在FPGA上实现CAN控制器难吗?有做成功了的吗?可以购买别人做好的IP核吗?IP核可靠吗?
feihufuture 发表于 2017-4-1 13:50 | 显示全部楼层
不适合自己设计,用芯片把
STARM 发表于 2017-4-4 01:06 | 显示全部楼层
https://opencores.org/project,can

Status
- Fixed problem when CAN was reset in SW at the inappropriate time. (November, 15, 2004)
- Fixed problem when 0xf was used for TSEG1. CAN tested up to 1 Mbps (October, 27, 2004)
- Tested in HW. Worked with another 11 boards in the system. (May, 12, 2004)
- Tested with the Bosch VHDL Reference System. All tests passed. (May, 12, 2004)
- Tested in HW. Worked with another board with SJA1000 CAN controller on it. (August, 18, 2003)
- 8051 interface added. (March, 12, 2003)
- Memory blocks for Actel APA devices added. Core size is approx. 40000 gates (from which internal fifos take 28000). (March, 1, 2003)
- Final version of the CAN controller is available. (February, 19, 2003)
- Initial version of the CAN controller is available. (February, 11, 2003)
- Status registers still under construction. (February, 11, 2003)
- Verification needed. Small test bench is written but needs to be improved. (February, 11, 2003)

Feedback
Authors are asking anybody that download this IP core to provide a feedback (bug report, wishlist, improvements).


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