module diff_manchester (datain,dataout,clkin,rst)
input [7:0]datain,[15:0]clkin,[15:0]rst;
output [15:0]dataout;
reg tmp,i;
always @(posedge clkin or negedge rst) //假定rst下降沿触发，clkin上升沿动作
if (rst) //定义rst=1触发复位
begin
datain <= 0;
dataout <=0;
tmp <=0;
end
else
begin
if (datain [7]==1'b0)
dataout [15,14]=2'b10;
else
dataout [15,14]=2'b01;
tmp=dataout [14]
for(i=1;i=7;i=i+1)
if(datain[7-i]=1)
begin
dataout[15-2*i]=tmp;
dataout[14-2*i]=~tmp;
end
else
begin
dataout[15-2*i]=~tmp;
dataout[14-2*i]=tmp;
end
end
endmodule
运行结果：Error (10170): Verilog HDL syntax error at diff_mancehsiter.v(2) near text "input"; expecting ";"
Info (12021): Found 0 design units, including 0 entities, in source file diff_mancehsiter.v
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 466 megabytes
Error: Processing ended: Sun Apr 16 08:51:07 2017
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
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