本帖最后由 epsmc 于 2010-5-7 15:25 编辑
这是一个全加器的例子，问题在后面红字标识
library ieee;
use ieee.std_logic_1164.all;
entity h_adder is
port(
a,b: in std_logic;
co,so:out std_logic
);
end h_adder;
architecture h_bhv of h_adder is
signal abc : std_logic_vector(1 downto 0);
begin
abc <= a & b;
process(abc)
begin
case abc is
when "00" =>so<='0'; co<='0';
when "01" =>so<='1'; co<='0';
when "10" =>so<='1'; co<='0';
when "11" =>so<='0'; co<='1';
when others =>null;
end case;
end process;
end h_bhv;
library ieee;
use ieee.std_logic_1164.all;
entity or2a is
port( a,b:in std_logic;
c:out std_logic
);
end or2a;
architecture or_bhv of or2a is
begin
c<= a or b;
end or_bhv;
library ieee;
use ieee.std_logic_1164.all;
entity f_adder is
port(ain,bin,cin: in std_logic;
sum,cout: out std_logic
);
end f_adder;
architecture f_bhv of f_adder is
component h_adder
port(
a,b: in std_logic;
co,so:out std_logic);
end component;
component or2a
port( a,b:in std_logic;
c:out std_logic);
end component;
signal d,e,f : std_logic;
begin
u1: h_adder port map(a=>ain, b=>bin, co=>d, so=>e);
u2: h_adder port map(a=>e, b=>cin, co=>f, so=>sum);
--u3: or2a port map(a=>d, b=>f, c=>cout); 可以利用标准库里的OR2例化吗？如何实现？例如：u3: or2 port map(a=>d, b=>f, c=>cout);
cout<= d or f;
end f_bhv; |
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