-- maibojishuqi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mbj is --定义实体为mbj
port(rst,fin,clk:in std_logic;
xs1,xs2,xs3:out std_logic_vector(3 downto 0));
end mbj;
architecture one of mbj is --结构体
begin
process(rst,fin,clk)
variable xh1,xh2,xh3:std_logic_vector(3 downto 0); --脉搏数的个十百位
variable en:bit;
variable s:integer range 0 to 20; --变量s为次数计数器
begin
if clk'event and clk='1' then
s:=s+1;
if s>15 then --计数时间在15s内
en:='0';
else en:='1';
end if;
end if;
if en='1' then
if rst='1' then --异步清零
xh1:=(others=>'0');
xh2:=(others=>'0');
xh3:=(others=>'0');
elsif fin'event and fin='1' then
xh1:=xh1+"0100"; --个位加1
if xh1>"1001" then --满十进位
xh1:=xh1-"1010";
if xh2="1001" then --满十进位
xh2:="0000";xh3:=xh3+1;
else xh2:=xh2+1;
end if;
else xh1:=xh1;
end if;
end if;
end if;
xs1<=xh1; --输出
xs2<=xh2;
xs3<=xh3;
end process;
end one;
上述计数器代码输入后编译无错误，rst、fin、clk 是画的波形。当仿真的时候出现下面的提示：
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./run.do PAUSED at line 16
麻烦各位大虾们帮忙解决下.........
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