FSMC对IS61LV25616的时序？

只看该作者 · 2010-6-6 22:02

哪位仁兄用过STM32成功控制IS61LV25616，能不能给个FSMC时序参数的设置，感激不尽。

只看该作者 · 2010-6-11 09:15

自己顶一下，以下是我的设置，读写均使用模式A，请指点。
  p1.FSMC_AddressSetupTime = 0;
  p1.FSMC_AddressHoldTime = 0;
  p1.FSMC_DataSetupTime = 5;
  p1.FSMC_BusTurnAroundDuration = 0;
  p1.FSMC_CLKDivision = 0;
  p1.FSMC_DataLatency = 0;
  p1.FSMC_AccessMode = FSMC_AccessMode_A;

  p2.FSMC_AddressSetupTime = 0;
  p2.FSMC_AddressHoldTime = 0;
  p2.FSMC_DataSetupTime = 3;
  p2.FSMC_BusTurnAroundDuration = 0;
  p2.FSMC_CLKDivision = 0;
  p2.FSMC_DataLatency = 0;
  p2.FSMC_AccessMode = FSMC_AccessMode_A;

  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Enable;
  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p1;
  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p2;

  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);

只看该作者 · 2010-6-11 09:15

自己顶一下，以下是我的设置，读写均使用模式A，请指点。
  p1.FSMC_AddressSetupTime = 0;
  p1.FSMC_AddressHoldTime = 0;
  p1.FSMC_DataSetupTime = 5;
  p1.FSMC_BusTurnAroundDuration = 0;
  p1.FSMC_CLKDivision = 0;
  p1.FSMC_DataLatency = 0;
  p1.FSMC_AccessMode = FSMC_AccessMode_A;

  p2.FSMC_AddressSetupTime = 0;
  p2.FSMC_AddressHoldTime = 0;
  p2.FSMC_DataSetupTime = 3;
  p2.FSMC_BusTurnAroundDuration = 0;
  p2.FSMC_CLKDivision = 0;
  p2.FSMC_DataLatency = 0;
  p2.FSMC_AccessMode = FSMC_AccessMode_A;

  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Enable;
  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p1;
  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p2;

  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);