小白第一次写HDB3编码程序,程序仿真过,没有问题;
但是第一次写,应该有很多地方需要改进和优化,请大家指点;
因为是自学的,没有人指正,就没有进步,请大家帮忙批评指正,非常感谢
module hdb3_code(clk,clr,e1_data_in,hdb3p_out,hdb3n_out,e1_data_out
);
input clk,clr;
input e1_data_in;
output hdb3p_out;
output hdb3n_out;
output e1_data_out;
// output [0:1]temp1;
// output [0:1]temp2;
// output [0:1]temp3;
// output [0:1]d1,d2,d3;
wire [0:1] e1_data_out;
reg hdb3p_out;
reg hdb3n_out;
reg [0:1]cnt;
reg [0:1] temp1=2'b00;
reg [0:1] temp2=2'b00;
// wire [0:1] temp2=2'b00;
reg [0:1] temp3=2'b00;
reg [0:1] d1=2'b00;
reg [0:1] d2=2'b00;
reg [0:1] d3=2'b00;
reg [0:1] d4=2'b00;
reg first_v;
reg count;
reg flag;
[email=always@(posedge]always@(posedge[/email] clk)
begin
if(clr)
begin
hdb3p_out<=1'b0;
hdb3n_out<=1'b0;
cnt<=2'b00;
count<=1'b0;
end
else
begin//插V
if (e1_data_in==1'b1)
begin
cnt<=2'b00;
temp1<=2'b01;
end
else
begin
if(cnt==2'b11)
begin
temp1<=2'b11;//11二进制表示V,检测到4个连‘0’时,将第4个0变成V码
cnt<=2'b00;
end
else
begin
temp1<=2'b00;
cnt<=cnt+1;
end
end
end
end
// assign temp2=d4;//不能用组合电路赋值向量
[email=always@(posedge]always@(posedge[/email] clk)//**(10)
begin
temp2<=d4;
// temp2<=d3;
d1<=temp1;
d2<=d1;
d3<=d2;
d4<=d3;
if(temp1==2'b11)
begin
if(first_v==1)
begin
if(count==0) d4<=2'b10;//两个V之间有偶数个1,**
else count<=1'b0;
end
else
begin
first_v<=1'b1;//第一次出现V码,要将first_v置1,同时将count置0;
count<=1'b0;
// temp2<=2'b00;
end
end
else if(temp1==2'b01)
begin
count<=count+1;
// temp2<=2'b01;
end
// else
// none;none在仿真时出错
end
[email=always@(posedge]always@(posedge[/email] clk)//极性反转
begin
if(temp2==2'b01)
begin
if(flag==1'b0)
begin
temp3<=2'b10; //10为正
hdb3p_out<=1'b1;
hdb3n_out<=1'b0;
flag<=1'b1;
end
else
begin
// hdb3n_out<=1'b1;//01为负
temp3<=2'b01;
hdb3p_out<=1'b0;
hdb3n_out<=1'b1;
flag<=1'b0;
end
end
else if(temp2==2'b10)
begin
if(flag==1'b0)
begin
temp3<=2'b10; //10为正
hdb3p_out<=1'b1;
hdb3n_out<=1'b0;
flag<=1'b1;
end
else
begin
// hdb3n_out<=1'b1;//01为负
temp3<=2'b01;
hdb3p_out<=1'b0;
hdb3n_out<=1'b1;
flag<=1'b0;
end
end
else if(temp2==2'b11)
begin
if(flag==1'b1)
begin
temp3<=2'b10;
hdb3p_out<=1'b1;
hdb3n_out<=1'b0;
end
else
begin
temp3<=2'b01;
hdb3p_out<=1'b0;
hdb3n_out<=1'b1;
end
end
else
begin
temp3<=2'b00;
hdb3p_out<=1'b0;
hdb3n_out<=1'b0;
end
end
assign e1_data_out=temp3;
endmodule |