下面这段code，启动一一对应的MMU！你对照MMU说明文档，应该比较容易能看懂
#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
(unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base, \
cacheable, bufferable, perm) \
CYG_MACRO_START \
register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
\
desc.word = 0; \
desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID; \
desc.section.imp = 1; \
desc.section.domain = 0; \
desc.section.c = (cacheable); \
desc.section.b = (bufferable); \
desc.section.ap = (perm); \
desc.section.base_address = (actual_base); \
*ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
= desc.word; \
CYG_MACRO_END
#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) \
{ int i; int j = abase; int k = vbase; \
for (i = size; i > 0 ; i--,j++,k++) \
{ \
ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access); \
} \
}
#define ARM_MMU_FINE(ttb_base, actual_base, virtual_base) \
CYG_MACRO_START \
register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc; \
\
desc.word = 0; \
desc.fine.id = ARM_MMU_FIRST_LEVEL_FINE_ID; \
desc.fine.sbz0 = 0; \
desc.fine.imp = 1; \
desc.fine.domain = 0; \
desc.fine.sbz1 = 0; \
desc.fine.base_address = (actual_base); \
*ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
= desc.word; \
CYG_MACRO_END
#define X_ARM_MMU_FINE(abase,vbase,size) \
{ int i; int j = abase; int k = vbase; \
for (i = size; i > 0 ; i--,j++,k++) \
{ \
ARM_MMU_FINE(ttb_base, j, k); \
} \
}
void hal_mmu_init(void)
{
unsigned long ttb_base = (unsigned long)__TTB_BASE_W55VA91;
unsigned long page_base = (unsigned long)__MM_PAGE_DESC;
unsigned long i;
memset((void*)ttb_base, 0, 0x4000);
// Set the TTB register
asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
// Set the Domain Access Control Register
i = ARM_ACCESS_TYPE_CLIENT(0) |
ARM_ACCESS_TYPE_NO_ACCESS(1) |
ARM_ACCESS_TYPE_NO_ACCESS(2) |
ARM_ACCESS_TYPE_NO_ACCESS(3) |
ARM_ACCESS_TYPE_NO_ACCESS(4) |
ARM_ACCESS_TYPE_NO_ACCESS(5) |
ARM_ACCESS_TYPE_NO_ACCESS(6) |
ARM_ACCESS_TYPE_NO_ACCESS(7) |
ARM_ACCESS_TYPE_NO_ACCESS(8) |
ARM_ACCESS_TYPE_NO_ACCESS(9) |
ARM_ACCESS_TYPE_NO_ACCESS(10) |
ARM_ACCESS_TYPE_NO_ACCESS(11) |
ARM_ACCESS_TYPE_NO_ACCESS(12) |
ARM_ACCESS_TYPE_NO_ACCESS(13) |
ARM_ACCESS_TYPE_NO_ACCESS(14) |
ARM_ACCESS_TYPE_NO_ACCESS(15);
asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
// First clear all TT entries - ie Set them to Faulting
//memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
/* Actual Virtual Size Attributes Function */
/* Base Base MB cached? buffered? access permissions */
#if 0
X_ARM_MMU_SECTION(SEC_NON_CACHEABLE_PHYS_ALL,SEC_NON_CACHEABLE_VIRT_ALL,SEC_NON_CACHEABLE_SIZE_ALL,
ARM_UNCACHEABLE,ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); //available all, :-( because I don't know nor flash access which address
X_ARM_MMU_SECTION(SEC_CACHEABLE_SDRAM_PHYS_BASE_0,SEC_CACHEABLE_SDRAM_VIRT_BASE_0,SEC_CACHEABLE_SDRAM_SIZE_0,
ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // cacheable SDRAM 0
X_ARM_MMU_SECTION(SEC_CACHEABLE_SDRAM_PHYS_BASE_1,SEC_CACHEABLE_SDRAM_VIRT_BASE_1,SEC_CACHEABLE_SDRAM_SIZE_1,
ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // cacheable SDRAM 1
X_ARM_MMU_SECTION(SEC_CACHEABLE_ROMFLASH_PHYS_BASE,SEC_CACHEABLE_ROMFLASH_VIRT_BASE,SEC_CACHEABLE_ROMFLASH_SIZE,
ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // cacheable ROM/FLASH
X_ARM_MMU_SECTION(SEC_CACHEABLE_EXTIO_PHYS_BASE,SEC_CACHEABLE_EXTIO_VIRT_BASE,SEC_CACHEABLE_EXTIO_SIZE,
ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // cacheable EXTIO I/O
//------------------------------------------------------------------------------------------------
X_ARM_MMU_SECTION(SEC_NON_CACHEABLE_SDRAM_PHYS_BASE_0,SEC_NON_CACHEABLE_SDRAM_VIRT_BASE_0,SEC_NON_CACHEABLE_SDRAM_SIZE_0,
ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // NON-cacheable SDRAM 0
X_ARM_MMU_SECTION(SEC_NON_CACHEABLE_SDRAM_PHYS_BASE_1,SEC_NON_CACHEABLE_SDRAM_VIRT_BASE_1,SEC_NON_CACHEABLE_SDRAM_SIZE_1,
ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // NON-cacheable SDRAM 1
X_ARM_MMU_SECTION(SEC_NON_CACHEABLE_ROMFLASH_PHYS_BASE,SEC_NON_CACHEABLE_ROMFLASH_VIRT_BASE,SEC_NON_CACHEABLE_ROMFLASH_SIZE,
ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // NON-cacheable ROM/FLASH
X_ARM_MMU_SECTION(SEC_NON_CACHEABLE_EXTIO_PHYS_BASE,SEC_NON_CACHEABLE_EXTIO_VIRT_BASE,SEC_NON_CACHEABLE_EXTIO_SIZE,
ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // NON-cacheable EXTIO I/O
//--------------------------------------------------------------------------------------------------
X_ARM_MMU_SECTION(SEC_LINE_BUF_RAM_PHYS_BASE,SEC_LINE_BUF_RAM_VIRT_BASE,SEC_LINE_BUF_RAM_SIZE,
ARM_UNCACHEABLE,ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // line buffer RAM
//X_ARM_MMU_SECTION(SAT_PALLET_RAM_PHYS_BASE,SAT_PALLET_RAM_VIRT_BASE,SAT_PALLET_RAM_SIZE,
// ARM_UNCACHEABLE,ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // SAT or Pallet RAM
//X_ARM_MMU_SECTION(ONCHIP_RAM_PHYS_BASE,ONCHIP_RAM_VIRT_BASE,ONCHIP_RAM_SIZE,
// ARM_UNCACHEABLE,ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // on-chip RAM
X_ARM_MMU_SECTION(SEC_ONCHIP_AHB_PHYS_BASE,SEC_ONCHIP_AHB_VIRT_BASE,SEC_ONCHIP_AHB_SIZE,
ARM_UNCACHEABLE,ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // on-chip AHB
X_ARM_MMU_SECTION(SEC_NON_CACHEABLE_NOR0_PHYS_BASE,SEC_NON_CACHEABLE_NOR0_VIRT_BASE,SEC_NON_CACHEABLE_NOR0_SIZE,
ARM_UNCACHEABLE,ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // nor0
/*
X_ARM_MMU_SECTION(SEC_NON_CACHEABLE_NOR1_PHYS_BASE,SEC_NON_CACHEABLE_NOR1_VIRT_BASE,SEC_NON_CACHEABLE_NOR1_SIZE,
ARM_UNCACHEABLE,ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // nor1
X_ARM_MMU_SECTION(SEC_NON_CACHEABLE_NOR2_PHYS_BASE,SEC_NON_CACHEABLE_NOR2_VIRT_BASE,SEC_NON_CACHEABLE_NOR2_SIZE,
ARM_UNCACHEABLE,ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // nor2 */
//X_ARM_MMU_SECTION(ONCHIP_APB_PHYS_BASE,ONCHIP_APB_VIRT_BASE,ONCHIP_APB_SIZE,
// ARM_UNCACHEABLE,ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); // on-chip APB
/*MMU reserved addr space for stack overflow detection*/
page_base >>=12;
X_ARM_MMU_FINE(page_base,SEC_MMU_RESERVED_VIRT_BASE,SEC_MMU_RESERVED_VIRT_SIZE);
#else
X_ARM_MMU_SECTION(0x0,0x0,0x7FE00000>>20, ARM_CACHEABLE,ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW);//cache region
X_ARM_MMU_SECTION(0x0,0x80000000>>20,0x7FE00000>>20, ARM_UNCACHEABLE,ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);//non-cache region
X_ARM_MMU_SECTION(0xFFE00000>>20,0xFFE00000>>20,0x200000>>20, ARM_UNCACHEABLE,ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);//non-cache region
#endif
} |
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