嵌入式DSP开发---dm642的视频口输出

void VP1_EDMA(int displayMode,unsigned int w,unsigned int h)
{
   
unsigned int i=0,k=0;
EDMA_Handle handle;
EDMA_Handle handle2;
EDMA_Config myEdmaConfig;

    handle= EDMA_open(EDMA_CHA_VP1EVTYA, EDMA_OPEN_RESET);
    handle2 = EDMA_allocTable(-1);
      
    if(displayMode==DISPLAY_640_480)
    {
   for(i=0;i<h;i++)
      {
          for(k=0;k<w;k++)
          {
              if(i<(h/2))
              {
                  if(k<(w/2))
                   *(unsigned int*)(0x81000000 + (w*i+k)*4 )=0xfc000;//0xfc000
                  else
                   *(unsigned int*)(0x81000000 + (w*i+k)*4 )=0x3fc0;//0xfc000
              }
              else
              {
                  if(k<(w/2))
                   *(unsigned int*)(0x81000000 + (w*i+k)*4 )=0x3f;//0xfc000
                  else
                   *(unsigned int*)(0x81000000 + (w*i+k)*4 )=0xfffc0;//0xfc000
              }   
          }
      }
         
       ////               PRI   ESIZE 2DS   SUM   2DD   DUM    link  FS
          myEdmaConfig.opt = 2<<29|0<<27|1<<26|1<<24|0<<23|0<<21|1<<1|0;
          myEdmaConfig.src = (Uint32)(0x81000000);
          myEdmaConfig.cnt = 0x01df0280;//FRMCNT  ELECNT (480*640)
          myEdmaConfig.dst = 0X78000020;//DST
          myEdmaConfig.idx = 0x0a000000;//FRMIDX  ELEIDX
          myEdmaConfig.rld = handle2;//ELERLD  LINK
}
         
       EDMA_config(handle,&myEdmaConfig);
    EDMA_config(handle2,&myEdmaConfig);
   
    //EDMA_setChannel(handle);//   *(unsigned int*)(0X01A0FFbC)=0x01000000;//触发通道56  第一次发送数据ESR  
    EDMA_setEvtPolarity(handle,EDMA_EVT_HIGHLOW);//*(unsigned int*)(0X01A0FF9c)=0x01000000; //EPRh Event polarity low register  1 falling edge ;0 rising edge
    EDMA_enableChaining(handle);  //*(unsigned int*)(0X01A0FFac)=0x01000000;//EDMA Channel Chain Enable high Register (CCERh) Field Descriptions
    EDMA_intEnable(handle);       //*(unsigned int*)(0X01A0FFa8)=0x01000000; //Channel interrupt enable high register
    EDMA_enableChannel(handle);  // *(unsigned int*)(0X01A0FFb4)=0x01000000;//EERH EDMA Event Enable high Register     

  
}

void VP1_Display(int displayMode)
{
       int h_total, v_total, h_actv, v_actv;
       if(displayMode==DISPLAY_640_480)
       {   
         h_total=800; v_total =525; h_actv = 640;  v_actv = 480;
  // h_total=1056; v_total=628; h_actv = 800;  v_actv = 600;
  // h_total=1344; v_total=806; h_actv = 1024; v_actv = 768;

   // GetCLK_307(25);

      *(unsigned int*)(0x01b3f018) = 0x10c0010c;//解锁
   *(unsigned int*)(0x01b3f000) = 0x28;//open vp1       使能位 bit6 vp2 bit5 vp1 bit4 vp0  bit3 i2c
   *(unsigned int*)(0x01b3f018) = 0x0;//锁定

      delay_loop3(0x2000);//延迟必须

   /////////////////////////////////////////////
     
   *(unsigned int*)(0x01C44000 + 0x004) = 0x05;//PCR  使能位bit2 vp1 enable   bit0 free run
   *(unsigned int*)(0x01C44000 + 0x024) = 0x00711511;//PDIR配置视频24个管脚输出   1 output   0缺省 input
   *(unsigned int*)(0x01C44000 + 0x038) = 0x00200000; //Video Port Pin Interrupt Enable Register
   *(unsigned int*)(0x01C44000 + 0x03c) = 0x00200000; //Video Port Pin Interrupt Polarity Register
   
   *(unsigned int*)(0x01C44000 + 0x0c8) = 0x17cf9; //VPIE
   *(unsigned int*)(0x01C44000 + 0x0c0) = 0x4032;/// VPCTL)  bit7DCLK  4 HS  5 VS 极性    1 enable

   *(unsigned int*)(0x01C44000 + 0x204) = 0x80000000;//vd reset
   delay_loop3(0x10000);
   ////////////////////////////////////////////////
  ///*
   *(unsigned int*)(0x01C44000 + 0x208) = ((v_total<<16)|h_total); //VDFRMSZ 525行 800个像素
   *(unsigned int*)(0x01C44000 + 0x20c) = (((h_total-1)<<16)|(h_actv-1));//VDHBLNK 800-640 -1  end start

   *(unsigned int*)(0x01C44000 + 0x210) = (((v_actv-2)<<16)|0);//VDVBLKS1 478 0  start
   *(unsigned int*)(0x01C44000 + 0x214) = (((v_total-1)<<16)|0);//VDVBLKE1 524 0   end

   *(unsigned int*)(0x01C44000 + 0x220) = ((0<<16)|0);//VDIMGOFF1
   *(unsigned int*)(0x01C44000 + 0x224) = ((v_actv<<16)|h_actv);//VDIMGSZ1  图像有效区域480 640

   *(unsigned int*)(0x01C44000 + 0x23c) = (((h_total-1)<<16)|(h_actv-1));//VDHSYNC 639-799

   *(unsigned int*)(0x01C44000 + 0x240) = (((v_actv-2)<<16)|0);//VDVSYNS1  478
   *(unsigned int*)(0x01C44000 + 0x244) = (((v_total-1)<<16)|0);//VDVSYNE1  524

   ////////////////////////////////////////////////////////////////////////////
      VP1_EDMA( displayMode,h_actv,v_actv);
     
   *(unsigned int*)(0x01C44000 + 0x230) = 0x00000000;//VDFLDT1
   *(unsigned int*)(0x01C44000 + 0x238) = 0x00001000|(h_actv/2);//VDTHRLD  50
   *(unsigned int*)(0x01C44000 + 0x254) = 0x00000000|(v_actv);//VDDISPEVT 1
   *(unsigned int*)(0x01C44000 + 0x260) = 0x00008006; //VDVINT

   *(unsigned int*)(0x01C44000 + 0x25c) = 0x3fc0;//VDDEFVAL 缺省数据设置 red  20位 6:8:6

   *(unsigned int*)(0x01C44000 + 0x204) = 0x400080c7;//VDCTL VCTL filed 选择   输出模式选择bit2-0   
   delay_loop3(0x80000);//延迟必须
   *(unsigned int*)(0x01C44000 + 0x204) = 0x000080d7;
   delay_loop3(0x80000);//延迟必须
   *(unsigned int*)(0x01C44000 + 0x204) = 0x000080c7;  
    ///////////////////////////////////////////暂停重新开始
   
   *(unsigned int*)(0X01A0FFb4)=0x00000000;//EERH EDMA Event Enable high Register
   delay_loop3(0x2000);
   *(unsigned int*)(0x01C44000 + 0x204) = 0x80000000;//vd reset
   delay_loop3(0x10000);
   *(unsigned int*)(0X01A0FFb4)=0x01000000;//EERH EDMA Event Enable high Register
   delay_loop3(0x2000);

   *(unsigned int*)(0x01C44000 + 0x204) = 0x80000000;//vd reset
   delay_loop3(0x10000);
   *(unsigned int*)(0x01C44000 + 0x208) = ((v_total<<16)|h_total); //VDFRMSZ 525行 800个像素
   *(unsigned int*)(0x01C44000 + 0x20c) = (((h_total-1)<<16)|(h_actv-1));//VDHBLNK 800-640 -1  end start

   *(unsigned int*)(0x01C44000 + 0x210) = (((v_actv-2)<<16)|0);//VDVBLKS1 478 0  start
   *(unsigned int*)(0x01C44000 + 0x214) = (((v_total-1)<<16)|0);//VDVBLKE1 524 0   end

   *(unsigned int*)(0x01C44000 + 0x220) = ((0<<16)|0);//VDIMGOFF1
   *(unsigned int*)(0x01C44000 + 0x224) = ((v_actv<<16)|h_actv);//VDIMGSZ1  图像有效区域480 640

   *(unsigned int*)(0x01C44000 + 0x23c) = (((h_total-1)<<16)|(h_actv-1));//VDHSYNC 639-799

   *(unsigned int*)(0x01C44000 + 0x240) = (((v_actv-2)<<16)|0);//VDVSYNS1  478
   *(unsigned int*)(0x01C44000 + 0x244) = (((v_total-1)<<16)|0);//VDVSYNE1  524
   ////////////////////////////////////////////////////////////////////////////
   *(unsigned int*)(0x01C44000 + 0x230) = 0x00000000;//VDFLDT1
   *(unsigned int*)(0x01C44000 + 0x238) = 0x00001000|(h_actv/2);//VDTHRLD  50
   *(unsigned int*)(0x01C44000 + 0x254) = 0x00000000|(v_actv);//VDDISPEVT 1
   *(unsigned int*)(0x01C44000 + 0x260) = 0x00008006; //VDVINT

   *(unsigned int*)(0x01C44000 + 0x25c) = 0x3fc0;//VDDEFVAL 缺省数据设置 red  20位 6:8:6

   *(unsigned int*)(0x01C44000 + 0x204) = 0x400080c7;//VDCTL VCTL filed 选择   输出模式选择bit2-0   
   delay_loop3(0x80000);//延迟必须
   *(unsigned int*)(0x01C44000 + 0x204) = 0x000080d7;
   delay_loop3(0x80000);//延迟必须
   *(unsigned int*)(0x01C44000 + 0x204) = 0x000080c7;
   
}

}