Verilog 编译出错，程序如下，那位能帮我解释一下问题在哪

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wangdaojin| 中级技术员

楼主 | 2010-9-10 14:32 | 只看该作者回帖奖励

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编译, verilog, TI, IO, TPU

用于CH341A的数据接收，

/*
*
*  File name:             communiction.v
*  File description:    PC with CPLD send and receive data frame to execute funtion
*  Operating environment:  QUARTUS II 9.0,MaxII EPM1270T144C5N
*
*/
module comunication (
  input  DS,
  input[7:0]  UsbData,
  output[7:0]  special_data,
  output[7:0]  function_data,
  output[7:0]  address_data,
  output[7:0]  operation_data1,
  output[7:0]  operation_data2,
  output[7:0]  operation_data3,
  output[7:0]  operation_data4,
  output[7:0]  operation_data5
  );
reg startCnt;
reg[3:0] ReceiveCount;
reg[7:0] mem1[3:0];
always @ (negedge DS)  begin
  if(ReceiveCount <= 4'h07)
begin
  mem1[ReceiveCount]<= UsbData[7:0];
  ReceiveCount <= ReceiveCount+1;
end
  else
begin
  if(ReceiveCount == 4'h07)
  begin
startCnt <= 1'b1;
ReceiveCount <= 4'h00;
  end
  else ReceiveCount <= 4'h00;
end
end
always @ (posedge startCnt) begin
  special_data <= mem1[0];
  function_data <= mem1[1];
  address_data <= mem1[2];
  operation_data1 <= mem1[3];
  operation_data2 <= mem1[4];
  operation_data3 <= mem1[5];
  operation_data4 <= mem1[6];
  operation_data5 <= mem1[7];
  startCnt <= 1'b0;
end
endmodule

编译出错信息提示  Error (10137): Verilog HDL Procedural Assignment error at communication.v(48): object "special_data" on left-hand side of assignment must have a variable data type

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