代码如下：
input input_data;
reg uploader;
always @ (posedge clk or posedge cs or posedge wr)
begin
if(cs)
......
else if(wr)
......
uploader <= input_data;
......
else
......
if(counter < uploader)
......
......
end
除了wr有效的时候更新uploader寄存器外，其它敏感变量变化时，uploader保持不变。
但是在另外的分支中需要用到uploader给另外一个寄存器赋值。
Warning (10240): Verilog HDL Always Construct warning at <modulename>(xx): inferring latch(es) for variable "uploader", which holds its previous value in one or more paths through the always construct
怎么消除这个警告？ |
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