关于reg型变量的问题

只看该作者 · 2010-11-8 16:47

/* the test of led
*------file information--------*
*file name: led.v
*set up time: 2010.11.8
*modify time:
*description: enable the led
*/
module led(
input clock_25M,       //the clock of
output [7:0] ledd
);
reg[22:0] cnt;
always @(posedge clock_25M)
begin
cnt<=cnt+1'b1;
end


wire led_clk=cnt[22];

reg[7:0] led_r;
reg[1:0] ch;
always @(posedge led_clk)
   begin
         ch<=ch+1'b1;
   case(ch)
   2'b00:led_r<=8'b11111100;
   2'b01:led_r<=8'b11110000;
   2'b10:led_r<=8'b11000011;
   2'b11:led_r<=8'b00001111;
   default:led_r<=8'b00111100;
   endcase
   end

assign ledd=led_r;
endmodule

reg型变量默认初始值为x，那么这段程序下载到FPGA中能否自动执行，希望各位大虾回答？？？？