LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY AD7714xiaosong IS
PORT(
AD7714sclk:OUT std_logic;
AD7714pol:OUT std_logic;
AD7714sync:OUT std_logic;
AD7714reset:OUT std_logic;
AD7714standby:OUT std_logic;
AD7714din:OUT std_logic;
AD7714cs:OUT std_logic;
AD7714drdy:IN std_logic;
AD7714dout:IN std_logic;
AD7714buffer:OUT std_logic;
clk:IN std_logic
);
END AD7714xiaosong;
ARCHITECTURE AD7714DATA OF AD7714xiaosong IS
SIGNAL Read_AD7714DATA:std_logic_vector(23 downto 0);
SIGNAL AD7714in_DATA:std_logic_vector(7 downto 0);
BEGIN
PROCESS(clk)
VARIABLE i:INTEGER RANGE 0 TO 6;
VARIABLE m:INTEGER RANGE 0 TO 23;
VARIABLE n:INTEGER RANGE 0 TO 6; --读数据
BEGIN
AD7714pol<='1'; --初始化
AD7714sync<='1';
AD7714standby<='1';
AD7714buffer<='1';
AD7714cs<='0';
AD7714reset<='1';
IF(clk'EVENT and clk='1')THEN
IF n<8 THEN
CASE n IS
WHEN 0 => AD7714in_DATA<="00100000";
WHEN 1 => AD7714in_DATA<="00010001";
WHEN 2 => AD7714in_DATA<="00110000";
WHEN 3 => AD7714in_DATA<="00000000";
WHEN 4 => AD7714in_DATA<="00010000";
WHEN 5 => AD7714in_DATA<="00100000";
WHEN 6 => AD7714in_DATA<="00011000"; --选择数据寄存器
WHEN OTHERS => AD7714in_DATA<="00011000";
END CASE;
END IF;
IF i< 8 THEN
AD7714sclk<='0';
AD7714din<=AD7714in_DATA(i); --把数据写入AD7714
i:=i+1;
AD7714sclk<='1';
ELSIF n=6 THEN
IF AD7714drdy='0' THEN --如果AD有新数据产生，就读AD输出数据
IF m<24 THEN
AD7714sclk<='0';
Read_AD7714DATA(m)<=AD7714dout;
i:=0;
AD7714sclk<='1';
END IF;
END IF;
ELSE i:=0;
n:=n+1;
END IF;
END IF;
END PROCESS;
END AD7714DATA; |
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