为什么在时钟的下降沿,计数值才变化呢?
时钟周期100us
下面是代码library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
entity cnt6 is
port
(clr,en,clk :in std_logic;
q :out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of cnt6 is
signal tmp :std_logic_vector(2 downto 0);
begin
process(clk)
-- variable q6:integer;
begin
if(clk'event and clk='1') then
if(clr='0')then
tmp<="000";
elsif(en='1') then
if(tmp="101")then
tmp<="000";
else
tmp<=unsigned(tmp)+'1';
end if;
end if;
end if;
q<=tmp;
-- qa<=q(0);
-- qb<=q(1);
-- qc<=q(2);
end process;
end rtl;
处女贴,恳请大家帮忙下,肯定会及时结贴的 |