为什么ALM_turn总是输出1，即使是在输入正确的情况下
module majority_new(U_P,U_N,V_P,V_N,W_P,W_N,
A_P,A_N,B_P,B_N,Z_P,Z_N,
Alm_Same,Alm_turn);
input U_P,U_N,V_P,V_N,W_P,W_N,
A_P,A_N,B_P,B_N,Z_P,Z_N;
output Alm_Same,Alm_turn;
reg Alm_Same,Alm_turn;
reg [0:2]UP;
reg [0:2]VP;
reg [0:2]WP;
reg [0:2]UVW;
reg [0:2]UVW_Shadow;
reg Init_over;
wire U,V,W,A,B,Z;
xor
X1(U,U_P,U_N),
X2(V,V_P,V_N),
X3(W,W_P,W_N),
X4(A,A_P,A_N),
X5(B,B_P,B_N),
X6(Z,Z_P,Z_N);
// UVW turn
always
begin
UP=U_P;
VP=V_P;
WP=W_P;
UVW=((UP<<2)|(VP<<1)|WP);
end
always
@(U_P or V_P or W_P)
begin
if(Init_over==1)
begin
case(UVW)
3'b001: begin
if((UVW_Shadow==3'b101)||(UVW_Shadow==3'b011))
Alm_turn=0;
else
Alm_turn=1;
end
3'b010: begin
if((UVW_Shadow==3'b011)||(UVW_Shadow==3'b110))
Alm_turn=0;
else
Alm_turn=1;
end
3'b011: begin
if((UVW_Shadow==3'b001)||(UVW_Shadow==3'b010))
Alm_turn=0;
else
Alm_turn=1;
end
3'b100: begin
if((UVW_Shadow==3'b110)||(UVW_Shadow==3'b101))
Alm_turn=0;
else
Alm_turn=1;
end
3'b101: begin
if((UVW_Shadow==3'b001)||(UVW_Shadow==3'b100))
Alm_turn=0;
else
Alm_turn=1;
end
3'b110: begin
if((UVW_Shadow==3'b010)||(UVW_Shadow==3'b100))
Alm_turn=0;
else
Alm_turn=1;
end
endcase
end
UVW_Shadow=UVW;
Init_over=1;
end
// Broken Line
always
begin
if((~U)||(~V)||(~W)||(~A)||(~B)||(~Z))
Alm_Same=1;
else
Alm_Same=0;
end
initial
begin
Alm_Same=0;
Alm_turn=0;
Init_over=0;
end
endmodule |
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