verilog 内部边沿触发

只看该作者 · 2011-1-26 21:37

本帖最后由 XLDZZ 于 2011-1-26 21:39 编辑

module digital(clk,clock_s,s1,s2,puls,ent);
input clk,s1,s2,ent;
output clock_s,puls;
reg clock_m=0,clock_s=0,puls;
reg[0:11] st_cunt;
integer cunt_m=0,cunt_s=0;
[email=always@(posedge]always@(posedge[/email] clk)
begin
if(cunt_m==4)
  begin
cunt_m<=0;
clock_m<=~clock_m;
  end
else
  begin
  cunt_m<=cunt_m+1;
end

if(clock_m==1)
  begin
  if(cunt_s==10)
begin
cunt_s<=0;
clock_s<=~clock_s;
  end
  else
cunt_s<=cunt_s+1;
  end
end

endmodule

想用clock_m的边沿触发下一级分频器，不知道如何使用（试过posedgeclock_m但是报错）

另外好像采用integer只能是32位的能否像vhdl一样限定长度

只看该作者 · 2011-1-28 09:56

好像在同一个always块里面不能使用在同一个always块的边沿触发信号

只看该作者 · 2011-2-8 12:35

自己写的按键检测消振（利用单稳消振）功能每按一下按键脉冲变化

module digital(clk,puls,en,s1,s2,led1,led2,clock);

input clk,en,s1,s2;
output puls,led1,led2,clock;
reg [8:0] cunt_s,cunt_on,cunt_off,temp_on=9'b100000000,temp_off=0;
reg [2:0 ] cunt_m;
reg [24:0] clock_s;
reg [24:0] cunt_l;
reg led1,led2,clock,**_k;
wire s1,s2,en,clk;
reg puls,**;
always @(posedge clk)//--------------puls occur
begin
if(**==1'b1) begin
if(cunt_on==9'b100101100) begin
cunt_on<=temp_on;
puls<=1'b1;
**<=1'b0;
end
else
begin
cunt_on<=cunt_on+1'b1;
end
end

if(!**) begin
if(cunt_off==9'b100101100) begin
cunt_off<=temp_off;
puls<=1'b0;
**<=1'b1;
led1<=~led1;
end
else
begin
cunt_off<=cunt_off+1'b1;
end
end
end

always@(posedge led2)
begin
if(temp_on<=9'b000111111) begin
temp_on<=9'b100000000;
end
else begin
temp_on<=temp_on-9'b000001111;
end
end

always@(posedge clk)//单稳消振
begin
if(s2==1'b0) begin
**_k=1'b1;
end

if(**_k==1'b1) begin
cunt_l<=cunt_l+1'b1;
if(cunt_l==24'b111111111111111111111111) begin
cunt_l<=24'b000000000000000000000000;
led2<=1'b1;
**_k<=1'b0;
end
else begin
cunt_l<=cunt_l+1'b1;
led2<=1'b0;
end
end
end
endmodule