/*---------------------------------------------------------------*/
/* Copyright(c) 2010 Shenzhen WFLY Technology Development Co.,Ltd. All rights reserved. */
/* Date Created :on June 21, 2010 , Designed By:qzq */
/* File Name :main.c */
/* Summary :main processing function */
/*----------------------------------------------------------------*/
/*---------------------------------------------------------------------------------*/
/* Include hear file */
/*---------------------------------------------------------------------*/
#include <stdio.h>
#include "NUC1xx.h"
#include "DrvGPIO.h"
/*----------------------------------------------------------------------------
Define variable
----------------------------------------------------------------------------*/
static uint32_t TimerCOUN=0;
/*----------------------------------------------------------------------------
Function subroutine
----------------------------------------------------------------------------*/
void Delay(uint32_t delayCnt)
{
while(delayCnt--)
{
__NOP();
__NOP();
}
}
uint32_t GetTDR(void)
{
return TIMER0->TDR;
}
/*----------------------------------------------------------------------------
Interrupt subroutine
----------------------------------------------------------------------------*/
void TMR0_IRQHandler(void) // Timer0 interrupt subroutine
{
TIMER0->TISR.TIF =1;
TimerCOUN++;
}
/*----------------------------------------------------------------------------
MAIN function
----------------------------------------------------------------------------*/
int32_t main (void)
{
int32_t TEMP=0;
NVIC_DisableIRQ(TMR0_IRQn); //Disable Timer0 interrupt
outpw(&TIMER0->TCSR ,0 ); //Disable Timer0
/* Step 1. Enable and Select Timer clock source */
SYSCLK->CLKSEL1.TMR0_S = 4; //Select 22Mhz for Timer0 clock source
SYSCLK->APBCLK.TMR0_EN =1; //Enable Timer0 clock source
/* Step 2. Select Operation mode */
TIMER0->TCSR.MODE=1; //Select periodic mode for operation mode
/* Step 3. Select Time out period = (Period of timer clock input) * (8-bit Prescale + 1) * (24-bit TCMP)*/
TIMER0->TCSR.PRESCALE=0; // Set Prescale [0~255]
TIMER0->TCMPR = 2765; // Set TCMPR [0~16777215]
// (1/22118400)*(0+1)*(2765)= 125.01usec or 7999.42Hz
/* Step 4. Enable interrupt */
TIMER0->TCSR.IE = 1;
TIMER0->TISR.TIF = 1; //Write 1 to clear for safty
NVIC_EnableIRQ(TMR0_IRQn); //Enable Timer0 Interrupt
/* Step 5. Enable Timer module */
TIMER0->TCSR.CRST = 1; //Reset up counter
TIMER0->TCSR.CEN = 1; //Enable Timer0
TIMER0->TCSR.TDR_EN=1; // Enable TDR function
while(1)
{
Delay(1000);
TEMP = GetTDR(); //Get value of up counter
if (TimerCOUN>40000) break; //Wait 5 seconds
}
NVIC_DisableIRQ(TMR0_IRQn); //Disable Timer0 interrupt
outpw(&TIMER0->TCSR ,0 ); //Disable Timer0
while(1);
}
/*---------------------------------------------------*/
/* */
/* Copyright (c) Nuvoton Technology Corp. All rights reserved. */
/* */
/*---------------------------------------------------*/
#ifndef __NUC1xx_H__
#define __NUC1xx_H__
/*
* ===========================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================
*/
typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers *******************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/****** ARMIKMCU Swift specific Interrupt Numbers *******************/
BOD_IRQn = 0,
WDT_IRQn = 1,
EINT0_IRQn = 2,
EINT1_IRQn = 3,
GPAB_IRQn = 4,
GPCDE_IRQn = 5,
PWMA_IRQn = 6,
PWMB_IRQn = 7,
TMR0_IRQn = 8,
TMR1_IRQn = 9,
TMR2_IRQn = 10,
TMR3_IRQn = 11,
UART0_IRQn = 12,
UART1_IRQn = 13,
SPI0_IRQn = 14,
SPI1_IRQn = 15,
SPI2_IRQn = 16,
SPI3_IRQn = 17,
I2C0_IRQn = 18,
I2C1_IRQn = 19,
CAN0_IRQn = 20,
CAN1_IRQn = 21,
SD_IRQn = 22,
USBD_IRQn = 23,
PS2_IRQn = 24,
ACMP_IRQn = 25,
PDMA_IRQn = 26,
I2S_IRQn = 27,
PWRWU_IRQn = 28,
ADC_IRQn = 29,
DAC_IRQn = 30,
RTC_IRQn = 31
/*!< maximum of 32 Interrupts are possible */
} IRQn_Type;
/*
* ====================
* ----------- Processor and Core Peripheral Section ------------------------
* ====================
*/
/* Configuration of the Cortex-M0 Processor and Core Peripherals */
#define __MPU_PRESENT 0 /*!< armikcmu does not provide a MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< armikcmu Supports 2 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
#include "system_NUC1xx.h" /* NUC1xx System */
#include "System\SysInfra.h"
/**
* Initialize the system clock
*
* @param none
* @return none
*
* @brief Setup the microcontroller system
* Initialize the PLL and update the SystemFrequency variable
*/
extern void SystemInit (void);
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/*--------------------- General Purpose Input and Ouptut ---------------------*/
typedef struct
{
__IO uint32_t PMD0:2;
__IO uint32_t PMD1:2;
__IO uint32_t PMD2:2;
__IO uint32_t PMD3:2;
__IO uint32_t PMD4:2;
__IO uint32_t PMD5:2;
__IO uint32_t PMD6:2;
__IO uint32_t PMD7:2;
__IO uint32_t PMD8:2;
__IO uint32_t PMD9:2;
__IO uint32_t PMD10:2;
__IO uint32_t PMD11:2;
__IO uint32_t PMD12:2;
__IO uint32_t PMD13:2;
__IO uint32_t PMD14:2;
__IO uint32_t PMD15:2;
} GPIO_PMD_T;
typedef __IO uint32_t GPIO_SCH_T;
typedef __IO uint32_t GPIO_DOUT_T;
typedef __IO uint32_t GPIO_DMASK_T;
typedef __IO uint32_t GPIO_PIN_T;
typedef __IO uint32_t GPIO_DBEN_T;
typedef __IO uint32_t GPIO_IMD_T;
typedef __IO uint32_t GPIO_IEN_T;
typedef __IO uint32_t GPIO_ISRC_T;
typedef struct
{
__IO uint32_t DBCLKSEL:4;
__IO uint32_t DBCLKSRC:1;
__IO uint32_t ICLK_ON:1;
__I uint32_t RESERVE:26;
} GPIO_DBNCECON_T;
typedef struct
{
GPIO_PMD_T PMD;
GPIO_SCH_T SCH;
GPIO_DOUT_T DOUT;
GPIO_DMASK_T DMASK;
GPIO_PIN_T PIN;
GPIO_DBEN_T DBEN;
GPIO_IMD_T IMD;
GPIO_IEN_T IEN;
GPIO_ISRC_T ISRC;
} GPIO_T; |
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