本帖最后由 wangjun403 于 2011-3-14 22:43 编辑
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity test is
port(
clk :in std_logic;
scl :inout std_logic;
sda :inout std_logic
);
end entity;
architecture structural of test is
begin
process(clk)
begin
if clk'event and clk='1' then
scl<='z';
end if;
end process;
end architecture structural;
quartus8.0编译提示的错误为：
Error (10316): VHDL error at test.vhd(21): character ''z'' used but not declared for type "std_logic"
modelsim的提示为：
Enumeration literal 'z' is type std.standard.character; expecting type ieee.std_logic_1164.std_logic.
std_logic类型里已经定了了'Z'的啊，为什么就不行呢？
请问大家这里是那里错了，要怎么修改？
最好可以详细解释下
PS：排除了端口类型设置的问题（inout）和赋值符号的问题(<=) |
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