看到datasheet中的一段话了：
When PWM is set High, DRVH will be set high after the adaptive non-overlap delay.When PWM is set low, DRVL will be set high after the adaptive non-overlap delay.
When the pWM is set to the mid state, DRVH will be set low, and after the adaptive non-overlap delay, DRVL will be set high. DRVL remain high during the ZCD blanking time. When the timer is expired, the SW pin will be monitored for zero cross detection. After the detection, the DRVL will be set low.
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