本帖最后由 widpj 于 2011-5-28 19:28 编辑
求指教，本人做的是一个计数器，但要求到一个使能端，即其中的EN,程序看似没错，但却不能编译，求大侠指教，不甚感激！！！
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity timecnt is
port(clk :in std_logic;
EN :in std_logic;
cnt1 : out std_logic_vector(3 downto 0);
cnt2 : out std_logic_vector(3 downto 0)
);
end timecnt;
architecture timecnt_1 of timecnt is
signal count1:std_logic_vector(3 downto 0);
signal count2:std_logic_vector(3 downto 0);
begin
process(clk,EN)
begin
if EN 'event and EN='0' then
count1<="0000";
count2<="0000";
if clk 'event and clk='1' then
if count2="1001" and count1="1001" then
count2<="0000";count1<="0000";
elsif count1="1001" then
count2<=count2+1;count1<="0000";
else count1<=count1+1;
end if;
end if;
end if;
cnt1<=count1;
cnt2<=count2;
end process;
end timecnt_1; |
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