本帖最后由 AutoESL 于 2011-10-1 14:40 编辑
Designing a pure, one-clock synchronous design is a luxury that few ASIC designers will ever know. Most of the ASICs that are ever designed are driven by multiple asynchronous clocks and require special data, control-signal and verification handling to insure the timely completion of a robust working design.
非常好的一篇论文,有兴趣的朋友值得一读.
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