本帖最后由 izefei 于 2011-6-9 09:31 编辑
本人是xilinx fpga初学者，平常用dual-port ram的时候都是直接调用IP核。今天尝试着自己编写了一个64X6的dual-port ram。可是第一种方法综合不过去，第二种综合之后占用很多资源。代码很短，望各位路过的大侠们指点下。
补充：
我开始采用的是如下方法，可综合不过去，错误提示为：
ERROR:Xst:2070 - If you are attempting to describe a dual-port block RAM with two separate write ports for signal <data>, please use a shared variable instead. Coding guidelines are provided in the user manual.
这上面的user manual我在xilinx官网上找了很长时间，也没找到相关东西。
process(clka)
begin
if(rising_edge(clka))then
if(wea='1')then
data(conv_integer(addra))<=dina;
else
douta<=data(conv_integer(addra));
end if;
end if;
end process;
process(clkb)
begin
if(rising_edge(clka))then
if(web='1')then
data(conv_integer(addrb))<=dinb;
else
doutb<=data(conv_integer(addrb));
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------------------
第二种方法：
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ram_dual IS
port (
clk: IN std_logic;
addra: IN std_logic_VECTOR(5 downto 0);
addrb: IN std_logic_VECTOR(5 downto 0);
dina: IN std_logic_VECTOR(5 downto 0);
dinb: IN std_logic_VECTOR(5 downto 0);
douta: OUT std_logic_VECTOR(5 downto 0);
doutb: OUT std_logic_VECTOR(5 downto 0);
wea: IN std_logic;
web: IN std_logic
);
END ram_dual;
ARCHITECTURE behavior OF ram_dual IS
type data_type is array(0 to 63) of std_logic_vector(5 downto 0);
signal data:data_type;
signal we:std_Logic_Vector(1 downto 0);
BEGIN
we<=wea & web;
process(clk)
begin
if(rising_edge(clk))then
case we is
when "11"=>
data(conv_integer(addra))<=dina;
data(conv_integer(addrb))<=dinb;
when "10"=>
data(conv_integer(addra))<=dina;
doutb<=data(conv_integer(addrb));
when "01"=>
douta<=data(conv_integer(addra));
data(conv_integer(addrb))<=dinb;
when "00"=>
douta<=data(conv_integer(addra));
doutb<=data(conv_integer(addrb));
when others=>Null;
end case;
end if;
end process;
END behavior; |
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