library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ss IS
PORT(clk,rst,add,sub:in std_logic;
clkout: out STD_LOGIC;
clk2khz:out STD_LOGIC);
end ss;
ARCHITECTURE behave OF ss IS
signal speed:integer range 1 to 5;
signal clk0 : std_logic;
signal clk1 : std_logic;
signal clk2 : std_logic;
signal clk3 : std_logic;
signal clk4 : std_logic;
begin
process ( clk )
variable cnt1 : integer range 0 to 250;
variable cnt2 : integer range 0 to 500;
variable cnt3 : integer range 0 to 625;
variable cnt4 : integer range 0 to 1250;
variable cnt5 : integer range 0 to 2500;
begin
if(clk'event and clk='1') then--f=1mhz
if cnt1 = 250 then --2khz
cnt1 := 0;
clk4 <= not clk4;
else cnt1:=cnt1+1;
end if;
if cnt2 = 500 then
cnt2 := 0;
clk3 <= not clk3;---------------------1kHz
else cnt2:=cnt2+1;
end if;
if cnt3 = 625 then
cnt3 := 0;
clk2 <= not clk2;---------------------800hz
else cnt3:=cnt3+1;
end if;
if cnt4 = 1250 then
cnt4 := 0;
clk1 <= not clk1;---------------------400hz
else cnt4:=cnt4+1;
end if;
if cnt5 = 2500 then
cnt5 := 0;
clk0<= not clk0;---------------------200hz
else cnt5:=cnt5+1;
end if;
end if;
end process;
process(add,sub,rst)
begin
if(rst='0') then speed<=3;
else
if(add='0')then
if speed<5 then
speed<=speed+1;
end if;
elsif(sub='0')then
if speed>1 then
speed<=speed-1;
end if;
end if;
end if;
end process;
process (clk)
begin
if(clk'event and clk='1') then
case speed is
when 1 =>clkout<=clk0;
when 2 =>clkout<=clk1;
when 3 =>clkout<=clk2;
when 4 =>clkout<=clk3;
when 5 =>clkout<=clk4;
when others=>clkout<=clk0;
end case;
clk2khz<=clk4;
end if;
end process;
end behave;