下面一段话来自 铁电存储器FM1808.pdf：
Memory Architecture
Users access 32,768 memory locations each with 8
data bits through a parallel interface. The complete
15-bit address specifies each of the 32,768 bytes
uniquely. Internally, the memory array is organized
into 32 blocks of 8Kb each. The 5 most-significant
address lines decode one of 32 blocks. This block
segmentation has no effect on operation, however the
user may wish to group data into blocks by its
endurance characteristics as explained on page 4.
截图如下：
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