本帖最后由 sunzhanshan 于 2011-10-7 17:48 编辑
The hardware includes the following:
2.SOLID PPGA Board
The following is a system picture:
The jump wire connection is as follows:
1. FPGA GPIO pin 13 -> UHF RFID GND.
2. FPGA GPIO pin 3 -> UHF RFID TX.
3. FPGA GPIO pin 4-> UHF RFID RX
FPGA的代码如下:
1.顶层模块:
module my_uart_top(clk,rst_n,rx,tx,key_input,txpc);
input clk; // 50MHz主时钟
input rst_n;
//低电平复位信号
input rx;
// FPGA接收数据信号
output tx;
// FPGA发送数据信号
input key_input;
//FPGA按键输入
output txpc;
//FPGA的RS232输出
wire bps_start;
//接收到数据后,波特率时钟启动信号置位
wire clk_bps;
// clk_bps的高电平为接收或者发送数据位的中间采样点
wire[7:0] rx_data;
//接收数据寄存器,保存直至下一个数据来到
wire rx_int;
//接收数据中断信号,接收到数据期间始终为高电平
//----------------------------------------------------
speed_select
speed_select(
.clk(clk), //波特率选择模块,接收和发送模块复用,不支持全双工通信
.rst_n(rst_n),
.bps_start(bps_start),
.clk_bps(clk_bps)
);
my_uart_rx
my_uart_rx(
.clk(clk), //接收数据模块
.rst_n(rst_n),
.rx(rx),
.clk_bps(clk_bps),
.bps_start(bps_start),
.rx_data(rx_data),
.rx_int(rx_int),
.txpc(txpc)
);
my_uart_tx
my_uart_tx(
.clk(clk), //发送数据模块
.rst_n(rst_n),
.tx(tx),
.key_input(key_input)
);
endmodule
2.波特率选择模块(此处跟RFID同步,为115200bps)
module speed_select(clk,rst_n,bps_start,clk_bps);
input clk; // 50MHz主时钟
input rst_n;
//低电平复位信号
input bps_start;
//接收到数据后,波特率时钟启动信号置位
output clk_bps;
// clk_bps的高电平为接收或者发送数据位的中间采样点
parameter
bps9600
= 5207,
//波特率为9600bps
bps19200
= 2603,
//波特率为19200bps
bps38400
= 1301,
//波特率为38400bps
bps57600
= 867,
//波特率为57600bps
bps115200
= 433;
//波特率为115200bps
parameter
bps9600_2 = 2603,
bps19200_2 = 1301,
bps38400_2 = 650,
bps57600_2 = 433,
bps115200_2 = 216;
reg[12:0] bps_para;
//分频计数最大值
reg[12:0] bps_para_2;
//分频计数的一半
reg[12:0] cnt;
//分频计数
reg clk_bps_r;
//波特率时钟寄存器
//----------------------------------------------------------
reg[2:0] uart_ctrl;
// uart波特率选择寄存器
//----------------------------------------------------------
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
uart_ctrl <= 3'd4;
//默认波特率为115200bps
end
else begin
case (uart_ctrl)
//波特率设置
3'd0:
begin
bps_para <= bps9600;
bps_para_2 <= bps9600_2;
end
3'd1:
begin
bps_para <= bps19200;
bps_para_2 <= bps19200_2;
end
3'd2:
begin
bps_para <= bps38400;
bps_para_2 <= bps38400_2;
end
3'd3:
begin
bps_para <= bps57600;
bps_para_2 <= bps57600_2;
end
3'd4:
begin
bps_para <= bps115200;
bps_para_2 <= bps115200_2;
end
default: ;
endcase
end
end
always @ (posedge clk or negedge rst_n)
if(!rst_n) cnt <= 13'd0;
else if(cnt<bps_para && bps_start) cnt <= cnt+1'b1;
//波特率时钟计数启动
else cnt <= 13'd0;
always @ (posedge clk or negedge rst_n)
if(!rst_n) clk_bps_r <= 1'b0;
else if(cnt==bps_para_2 && bps_start) clk_bps_r <= 1'b1;
// clk_bps_r高电平为接收或者发送数据位的中间采样点
else clk_bps_r <= 1'b0;
assign clk_bps = clk_bps_r;
endmodule |