问： 用NOR flash配置时，CCLK 怎么接？
ug380, p48 写到:"The CCLK net requires Thevenin parallel termination. For more details, see Board Layout for Configuration Clock (CCLK), page 52."
p52:"In master configuration modes, when unused in the design, the CCLK pin is not
driven. It is recommended to drive this pin to a logic level to prevent the pin from
floating."
这样说，CCLK应该上拉，但是p49写到：
“9. The CCLK outputs are not used to connect to flash but are used to sample flash read
data during configuration. All timings are referenced to CCLK. The CCLK pin must
not be driven or tied High or Low.”
表示要悬空，到底怎样？
答：这个问题还是真的很细。
在P50： "1. CCLK is output in BPI modes. The parallel NOR flash does not require CCLK, but the Spartan-6 FPGA uses the rising edge of CCLK to sample D[n:0] pins."
就是说nor flash配置是不需要CCLK的，应该悬空
答：这个问题还是真的很细。
在P50： "1. CCLK is output in BPI modes. The parallel NOR flash does not require CCLK, but the Spartan-6 FPGA uses the rising edge of CCLK to sample D[n:0] pins."
就是说nor ...
hjjnet 发表于 2011-10-16 00:57
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