Introduction
The LogiCORE™ IP Media Independent Interface (MII)
to Reduced Media Independent (RMII) design provides
the RMII between RMII-compliant ethernet physical
media devices (PHY) and Xilinx 10/100 Mb/s ethernet
cores such as the XPS LL TEMAC and XPS Ethernet
Lite. These cores provide the traditional MII that
requires sixteen signals to communicate with an
ethernet PHY. The MII to RMII core accepts the sixteen
signal MII interface and provides a six or seven signal
interface to an RMII compliant PHY. Additionally, a
fixed 50 MHz reference clock synchronizes the MII to
RMII core with both interfaces. The 50 MHz reference
clock can be provided by a source external to the host
FPGA, or generated within the host FPGA. The MII to
RMII core follows the specification defined by the RMII
Consortium (version 1.0).
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