drivers/misc/nuc970-sc.c文件
static int sc_open(struct inode *inode, struct file *filp)
{
int ret, intf;
for(intf = 0; intf < SC_INTF; intf++)
if(MINOR(inode->i_rdev) == sc[intf].minor) {
break;
}
mutex_lock(&sc[intf].lock);
if(sc->open == 1) {
mutex_unlock(&sc[intf].lock);
return -EBUSY;
}
filp->private_data = (void *)&sc[intf];
if(intf == 0) {
sc[intf].clk = clk_get(NULL, "smc0");
sc[intf].eclk = clk_get(NULL, "smc0_eclk");
} else {
sc[intf].clk = clk_get(NULL, "smc1");
sc[intf].eclk = clk_get(NULL, "smc1_eclk");
}
if (IS_ERR(sc[intf].clk)) {
printk("failed to get sc clock\n");
ret = PTR_ERR(sc[intf].clk);
goto out2;
}
if (IS_ERR(sc[intf].eclk)) {
printk("failed to get sc eclock\n");
ret = PTR_ERR(sc[intf].eclk);
goto out2;
}
clk_prepare(sc[intf].clk);
clk_enable(sc[intf].clk);
clk_prepare(sc[intf].eclk);
clk_enable(sc[intf].eclk);
clk_set_rate(sc[intf].eclk, 4000000); // Set SC clock to 4MHz
if(sc[intf].pwrinv) {
__raw_writel(__raw_readl(sc[intf].base + REG_SC_PINCTL) | SC_PINCTL_PWRINV, sc[intf].base + REG_SC_PINCTL);
}
if(sc[intf].cdlvl == 0) {
__raw_writel(__raw_readl(sc[intf].base + REG_SC_CTL) | SC_CTL_CDLV, sc[intf].base + REG_SC_CTL);
}
// enable SC engine
__raw_writel(__raw_readl(sc[intf].base + REG_SC_CTL) | SC_CTL_SCEN, sc[intf].base + REG_SC_CTL);
if (request_irq(sc[intf].irq, nuc970_sc_interrupt,
0x0, "nuc970-sc", (void *)&sc[intf])) {
printk("register irq failed %d\n", sc[intf].irq);
ret = -EAGAIN;
goto out1;
}
sc[intf].open = 1;
mutex_unlock(&sc[intf].lock);
return 0;
out1:
free_irq(sc[intf].irq, (void *)&sc[intf]);
out2:
mutex_unlock(&sc[intf].lock);
return ret;
}
if(sc->open == 1) //会导致SC0 open时 SC1 open 错误,修改为 if(sc[intf].open == 1) 即可
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