各位大佬，我目前正在学习5502的开发板，准备利用McBSP和DMA的pingpong传输来分别传输linein口输入的音频信号，程序我贴在下方了，小弟实在不知道问题出在哪了，相应的数组根本没有数据输入进，不知道是中断出了问题还是DMA部分有问题，还希望大家能帮我看一下，帮我解答一下，真的很着急！！！
***************************************************************************************/
#include <stdio.h>
#include <csl_dma.h>
#include <csl_pll.h>
#include <csl_chip.h>
#include <csl_irq.h>
#include <csl_gpt.h>
#include <math.h>
#include <csl_emif.h>
#include <csl_emifBhal.h>
#include <csl_gptdat.h>
#include <csl_gpthal.h>
#include <csl_uart.h>
#include <csl_uarthal.h>
#include <csl_mcbsp.h>
#include <LMS.h>
#define SPCR10_VAL 0x0000
#define SPCR20_VAL 0x0220
//2 words per frame
#define RCR10_VAL 0x0140
#define RCR20_VAL 0x04
//2 words per frame
#define XCR10_VAL 0x0140
#define XCR20_VAL 0x04
#define PCR0_VAL 0x01
#define VOL1 0x81
#define VOL2 0x82
#define L_LINE_VOLUME 0x00
#define R_LINE_VOLUME 0x01
#define L_HEADPHONE_VOLUME 0x02
#define R_HEADPHONE_VOLUME 0x03
#define A_AUDIO_PATH 0x04
#define D_AUDIO_PATH 0x05
#define POWER_CON 0x06
#define D_AUDIO_INTERFACE 0x07
#define SAMPLE_RATE 0x08
#define D_INTERFACE_ACT 0x09
#define RESET 0x0f
#define SetAICCS 0x40 //data[6]=1，与CPLD的译码有关，可参考CPLD的源程序
#define ClrAICCS 0xBF //data[6]=0
#define SetSIDIN 0x20 //data[5]=1
#define ClrSIDIN 0xDF //data[5]=0
#define SetSCLK 0x10 //data[4]=1
#define ClrSCLK 0xEF //data[4]=0 SICLK
#define LedReg (*((volatile Uint16 *)0x41FF)) //CPLD引脚LED的地址
#define SysReg (*((volatile Uint16 *)0x8010)) //AIC的地址
#define KeyReg (*((volatile Uint16 *)0x44FF)) //CPLD引脚按键的地址
//---------Global constants---------
#define N 128
//---------Global data definition---------
/* Define transmit and receive buffers */
#pragma DATA_SECTION(in_1,"dmaMem")
Uint16 in_1[N];
#pragma DATA_SECTION(in_2,"dmaMem")
Uint16 in_2[N];
#pragma DATA_SECTION(out_1,"dmaMem")
Uint16 out_1[N];
#pragma DATA_SECTION(out_2,"dmaMem")
Uint16 out_2[N];
//int pingrcv[N], pongrcv[N], pingxmt[N], pongxmt[N],Leftchannel_Buffer[N],Rightchannel_Buffer[N];
int noise[N], error[N], out_y[N]; //存储待处理信号数组
int xfreebuf,rfreebuf,xpongbuf,rpongbuf,xpingbuf,rpingbuf;
Uint16 ping_buff_offset = (Uint16) &in_1[0];
Uint16 pong_buff_offset = (Uint16) &in_2[0];
Uint16 out1_offset = (Uint16) &out_1[0];
Uint16 out2_offset = (Uint16) &out_2[0];
//int xmtEventId,rcvEventId;
Uint16 dmaXmtIsr_count=0; //计数进入传送中断的次数
Uint16 dmaRcvIsr_count=0; //计数进入接收中断的次数
int i,j;
static int PingPong;
#define PING 0
#define PONG 1
extern void delay(Uint32 k);
extern void InitAic23(void);
extern void WriteAic23(Uint16 addr, Uint16 dat);
/*EMIF_Config MyEmifConfig = {
EMIF_GBLCTL1_RMK( // EMIF Global Control Register 1
EMIF_GBLCTL1_NOHOLD_HOLD_ENABLED, // Hold enable
EMIF_GBLCTL1_EK1HZ_EK1EN, // High-Z control
EMIF_GBLCTL1_EK1EN_ENABLED // ECLKOUT1 Enable
),
EMIF_GBLCTL2_RMK( // EMIF Global Control Register 2
EMIF_GBLCTL2_EK2RATE_1XCLK, // ECLKOUT2 Rate
EMIF_GBLCTL2_EK2HZ_EK2EN, // EK2HZ = 0, ECLKOUT2 is driven with value specified by EKnEN during
EMIF_GBLCTL2_EK2EN_DISABLED // ECLKOUT2 Enable (enabled by default)
),
EMIF_CE1CTL1_RMK( // CE1 Space Control Register 1
EMIF_CE1CTL1_TA_DEFAULT,
EMIF_CE1CTL1_READ_STROBE_DEFAULT,
EMIF_CE1CTL1_MTYPE_DEFAULT,
EMIF_CE1CTL1_WRITE_HOLD_MSB_DEFAULT,
EMIF_CE1CTL1_READ_HOLD_DEFAULT
),
EMIF_CE1CTL2_RMK( // CE1 Space Control Register 2
EMIF_CE1CTL2_WRITE_SETUP_DEFAULT,
EMIF_CE1CTL2_WRITE_STROBE_DEFAULT,
EMIF_CE1CTL2_WRITE_HOLD_DEFAULT,
EMIF_CE1CTL2_READ_SETUP_DEFAULT
),
EMIF_CE0CTL1_RMK( // CE0 Space Control Register 1
EMIF_CE0CTL1_TA_DEFAULT,
EMIF_CE0CTL1_READ_STROBE_DEFAULT,
EMIF_CE0CTL1_MTYPE_16BIT_ASYNC,
EMIF_CE0CTL1_WRITE_HOLD_MSB_DEFAULT,
EMIF_CE0CTL1_READ_HOLD_DEFAULT
),
EMIF_CE0CTL2_RMK( // CE0 Space Control Register 2
EMIF_CE0CTL2_WRITE_SETUP_DEFAULT,
EMIF_CE0CTL2_WRITE_STROBE_DEFAULT,
EMIF_CE0CTL2_WRITE_HOLD_DEFAULT,
EMIF_CE0CTL2_READ_SETUP_DEFAULT
),
EMIF_CE2CTL1_RMK( // CE2 Space Control Register 1
EMIF_CE2CTL1_TA_DEFAULT, // Not use for SDRAM (asynchronous memory types only)
EMIF_CE2CTL1_READ_STROBE_DEFAULT, // Read strobe width
EMIF_CE2CTL1_MTYPE_32BIT_SDRAM, // 32-bit-wide SDRAM
EMIF_CE2CTL1_WRITE_HOLD_DEFAULT, // Write hold width
EMIF_CE2CTL1_READ_HOLD_DEFAULT // Read hold width
),
EMIF_CE2CTL2_RMK( // CE2 Space Control Register 2
EMIF_CE2CTL2_WRITE_SETUP_DEFAULT, // Write setup width
EMIF_CE2CTL2_WRITE_STROBE_DEFAULT, // Write strobe width
EMIF_CE2CTL2_WRITE_HOLD_DEFAULT, // Write hold width
EMIF_CE2CTL2_READ_SETUP_DEFAULT // Read setup width
),
EMIF_CE3CTL1_RMK( // CE3 Space Control Register 1
EMIF_CE3CTL1_TA_DEFAULT, // Not use for SDRAM (asynchronous memory types only)
EMIF_CE3CTL1_READ_STROBE_DEFAULT, // Read strobe width
EMIF_CE2CTL1_MTYPE_32BIT_SDRAM, // 32-bit-wide SDRAM
EMIF_CE3CTL1_WRITE_HOLD_DEFAULT, // Write hold width
EMIF_CE3CTL1_READ_HOLD_DEFAULT // Read hold width
),
EMIF_CE3CTL2_RMK( // CE3 Space Control Register 2
EMIF_CE3CTL2_WRITE_SETUP_DEFAULT, // Write setup width
EMIF_CE3CTL2_WRITE_STROBE_DEFAULT, // Write strobe width
EMIF_CE3CTL2_WRITE_HOLD_DEFAULT, // Write hold width
EMIF_CE3CTL2_READ_SETUP_DEFAULT // Read setup width
),
EMIF_SDCTL1_RMK( // SDRAM Control Register 1
EMIF_SDCTL1_TRC_OF(6), // Specifies tRC value of the SDRAM in EMIF clock cycles.
EMIF_SDCTL1_SLFRFR_DISABLED // Auto-refresh mode
),
EMIF_SDCTL2_RMK( // SDRAM Control Register 2
0x11, // 4 banks,11 row address, 8 column address
EMIF_SDCTL2_RFEN_ENABLED, // Refresh enabled
EMIF_SDCTL2_INIT_INIT_SDRAM,
EMIF_SDCTL2_TRCD_OF(1), // Specifies tRCD value of the SDRAM in EMIF clock cycles
EMIF_SDCTL2_TRP_OF(1) // Specifies tRP value of the SDRAM in EMIF clock cycles
),
0x61B, // SDRAM Refresh Control Register 1
0x0300, // SDRAM Refresh Control Register 2
EMIF_SDEXT1_RMK( // SDRAM Extension Register 1
EMIF_SDEXT1_R2WDQM_1CYCLE,
EMIF_SDEXT1_RD2WR_3CYCLES,
EMIF_SDEXT1_RD2DEAC_1CYCLE,
EMIF_SDEXT1_RD2RD_1CYCLE,
EMIF_SDEXT1_THZP_OF(1), // tPROZ2=2
EMIF_SDEXT1_TWR_OF(0), //
EMIF_SDEXT1_TRRD_2CYCLES,
EMIF_SDEXT1_TRAS_OF(4),
EMIF_SDEXT1_TCL_2CYCLES
),
EMIF_SDEXT2_RMK( // SDRAM Extension Register 2
EMIF_SDEXT2_WR2RD_0CYCLES,
EMIF_SDEXT2_WR2DEAC_1CYCLE,
0,
EMIF_SDEXT2_R2WDQM_1CYCLE
),
EMIF_CE1SEC1_DEFAULT, // CE1 Secondary Control Register 1
EMIF_CE0SEC1_DEFAULT, // CE0 Secondary Control Register 1
EMIF_CE2SEC1_DEFAULT, // CE2 Secondary Control Register 1
EMIF_CE3SEC1_DEFAULT, // CE3 Secondary Control Register 1
EMIF_CESCR_DEFAULT // CE Size Control Register
}; */
MCBSP_Config ConfigLoopBack16= {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF, /* DLB = 1 */
MCBSP_SPCR1_RJUST_RZF, /* RJUST = 2 MCBSP_SPCR1_RJUST_RZF, */
MCBSP_SPCR1_CLKSTP_DISABLE, /* CLKSTP = 0 */
MCBSP_SPCR1_DXENA_NA, /* DXENA = 0 */
MCBSP_SPCR1_ABIS_DISABLE, /* ABIS = 0 */
MCBSP_SPCR1_RINTM_RRDY, /* RINTM = 0 */
0, /* RSYNCER = 0 */
MCBSP_SPCR1_RRST_ENABLE /* RRST = 0 */
),
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_YES, /* ? FREE = 1 MCBSP_SPCR2_FREE_NO, */
MCBSP_SPCR2_SOFT_NO, /* SOFT = 0 */
MCBSP_SPCR2_FRST_FSG, /* FRST = 0 */
MCBSP_SPCR2_GRST_CLKG, /* GRST = 0 */
MCBSP_SPCR2_XINTM_XRDY, /* XINTM = 0 */
0, /* XSYNCER = N/A */
MCBSP_SPCR2_XRST_ENABLE /* XRST = 0 */
),
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(1), /* RFRLEN1 = 0 MCBSP_RCR1_RFRLEN1_OF(0) */
MCBSP_RCR1_RWDLEN1_16BIT /* RWDLEN1 = 5 */
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE, /* RPHASE = 0 */
MCBSP_RCR2_RFRLEN2_OF(0), /* RFRLEN2 = 0 */
MCBSP_RCR2_RWDLEN2_8BIT, /* RWDLEN2 = 0 */
MCBSP_RCR2_RCOMPAND_MSB, /* RCOMPAND = 0 */
MCBSP_RCR2_RFIG_YES, /* RFIG = 1 */
MCBSP_RCR2_RDATDLY_0BIT /* RDATDLY = 0 */
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(0), /* XFRLEN1 = 0 */
MCBSP_XCR1_XWDLEN1_16BIT /* XWDLEN1 = 5 */
),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE, /* XPHASE = 0 */
MCBSP_XCR2_XFRLEN2_OF(0), /* XFRLEN2 = 0 */
MCBSP_XCR2_XWDLEN2_8BIT, /* XWDLEN2 = 0 */
MCBSP_XCR2_XCOMPAND_MSB, /* XCOMPAND = 0 */
MCBSP_XCR2_XFIG_NO, /* XFIG = 0 MCBSP_XCR2_XFIG_YES */
MCBSP_XCR2_XDATDLY_0BIT /* XDATDLY = 0 */
),
MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(1), /* FWID = 1 */
MCBSP_SRGR1_CLKGDV_OF(1) /* CLKGDV = 1 */
),
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE, /* FREE = 0 */
MCBSP_SRGR2_CLKSP_RISING, /* CLKSP = 0 */
MCBSP_SRGR2_CLKSM_INTERNAL, /* CLKSM = 1 */
MCBSP_SRGR2_FSGM_DXR2XSR, /* FSGM = 0 */
MCBSP_SRGR2_FPER_OF(15) /* FPER = 0 */
),
MCBSP_MCR1_DEFAULT,
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
//MCBSP_PCR_IDLEEN_RESET, /* IDLEEN = 0 */
MCBSP_PCR_XIOEN_SP, /* XIOEN = 0 */
MCBSP_PCR_RIOEN_SP, /* RIOEN = 0 */
MCBSP_PCR_FSXM_INTERNAL, /* FSXM = 1 */
MCBSP_PCR_FSRM_EXTERNAL, /* FSRM = 0 */
MCBSP_PCR_CLKXM_OUTPUT, /* CLKXM = 1 */
MCBSP_PCR_CLKRM_INPUT, /* CLKRM = 0 */
MCBSP_PCR_SCLKME_NO, /* SCLKME = 0 */
0, /* DXSTAT = N/A */
MCBSP_PCR_FSXP_ACTIVEHIGH, /* FSXP = 0 */
MCBSP_PCR_FSRP_ACTIVEHIGH, /* FSRP = 0 */
MCBSP_PCR_CLKXP_RISING, /* CLKXP = 0 */
MCBSP_PCR_CLKRP_FALLING /* CLKRP = 0 */
),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};
/* Create DMA Receive Side Configuration */
DMA_Config dmaRcvConfig = {
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_DARAMPORT1,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_PERIPH,
DMA_DMACSDP_DATATYPE_16BIT
), /* DMACSDP */
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_POSTINC,
DMA_DMACCR_SRCAMODE_CONST,
DMA_DMACCR_ENDPROG_ON,
DMA_DMACCR_WP_DEFAULT,
DMA_DMACCR_REPEAT_OFF, //DMA_DMACCR_REPEAT_OFF,
DMA_DMACCR_AUTOINIT_ON, //DMA_DMACCR_AUTOINIT_OFF, //Auto initialization bit :-
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_LOW,
DMA_DMACCR_FS_DISABLE, //DMA_DMACCR_FS_ELEMENT, //Frame/Element Sync :-单元事件同步
DMA_DMACCR_SYNC_REVT0
//DMA_DMACCR_SYNC_REVT1 //DMA_DMACCR_SYNC_XEVT1 //Synchronization control :-McBSP1 Transmit Event(XEVT1)
), /* DMACCR */
DMA_DMACICR_RMK(
DMA_DMACICR_AERRIE_ON,
DMA_DMACICR_BLOCKIE_OFF, //DMA_DMACICR_BLOCKIE_ON, //Whole block interrupt enable :-块传输完成后中断使能
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_ON, //DMA_DMACICR_FRAMEIE_OFF, //Whole frame interrupt enable :-
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
), /* DMACICR */
(DMA_AdrPtr)(MCBSP_ADDR(DRR10)), /* DMACSSAL 源地址低位 */
0, /* DMACSSAU 源地址高位 */
(DMA_AdrPtr)&in_1[0], /* DMACDSAL 目的地址低位 */
0, /* DMACDSAU 目的地址高位 */
N,//2 /* DMACEN 一帧内数据长度 16*2 两个数据一个帧 */
1,//N/2 /* DMACFN 帧数大小 */
0, /* DMACFI */
0 /* DMACEI */
};
/* Create DMA Transmit Side Configuration */
DMA_Config dmaXmtConfig = {
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST,
DMA_DMACSDP_DSTPACK_OFF,
DMA_DMACSDP_DST_PERIPH,
DMA_DMACSDP_SRCBEN_NOBURST,
DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_DARAMPORT0,
DMA_DMACSDP_DATATYPE_16BIT
), /* DMACSDP */
DMA_DMACCR_RMK(
DMA_DMACCR_DSTAMODE_CONST,
DMA_DMACCR_SRCAMODE_POSTINC,
DMA_DMACCR_ENDPROG_ON,
DMA_DMACCR_WP_DEFAULT,
DMA_DMACCR_REPEAT_OFF,
DMA_DMACCR_AUTOINIT_OFF, //DMA_DMACCR_AUTOINIT_ON, //Auto initialization bit :-
DMA_DMACCR_EN_STOP,
DMA_DMACCR_PRIO_LOW,
DMA_DMACCR_FS_DISABLE,
DMA_DMACCR_SYNC_XEVT0
//DMA_DMACCR_SYNC_XEVT1
), /* DMACCR */
DMA_DMACICR_RMK(
DMA_DMACICR_AERRIE_ON,
DMA_DMACICR_BLOCKIE_OFF, //DMA_DMACICR_BLOCKIE_ON, //Whole block interrupt enable :-块传输完成后中断使能
DMA_DMACICR_LASTIE_OFF,
DMA_DMACICR_FRAMEIE_ON, //DMA_DMACICR_FRAMEIE_OFF, //Whole frame interrupt enable :-
DMA_DMACICR_FIRSTHALFIE_OFF,
DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF
), /* DMACICR */
(DMA_AdrPtr)&out_1[0], /* DMACSSAL */
0, /* DMACSSAU */
(DMA_AdrPtr)(MCBSP_ADDR(DXR10)), /* DMACDSAL */
0, /* DMACDSAU */
N, /* DMACEN */
1, /* DMACFN */
0, /* DMACFI */
0 /* DMACEI */
};
/* Define a DMA_Handle object to be used with DMA_open function */
DMA_Handle hDmaRcv, hDmaXmt;
/* Define a MCBSP_Handle object to be used with MCBSP_open function */
MCBSP_Handle hMcbsp;
//volatile Uint16 transferComplete = FALSE;
//Uint16 err = 0;
Uint16 volume,tAicRegs;
Uint16 old_intm;
Uint16 xmtEventId, rcvEventId;
//---------Function prototypes---------
/* Reference start of interrupt vector table */
/* This symbol is defined in file, vectors.s55 */
extern void VECSTART(void);
/* Protoype for interrupt functions */
interrupt void dmaXmtIsr(void);
interrupt void dmaRcvIsr(void);
void taskFxn(void);
//---------main routine---------
void main(void)
{
//Uint16 i;
int k;
for(k=0; k<128; k++) { in_1[k] = 0x00000000; }
for(k=0; k<128; k++) { in_2[k] = 0x00000000; }
for(k=0; k<128; k++) { out_1[k] = 0x00000000; }
for(k=0; k<128; k++) { out_2[k] = 0x00000000; }
/* Initialize CSL library - This is REQUIRED !!! */
CSL_init();
/* Set IVPD/IVPH to start of interrupt vector table */
IRQ_setVecs((Uint32)(&VECSTART));
PLL_setFreq(1, 0x6, 0, 1, 3, 3, 0);
CHIP_RSET(XBSR,0x0001);
//EMIF_config(&MyEmifConfig);
tAicRegs=0xFF;
SysReg=tAicRegs;
InitAic23();
delay(500);
volume=108;
WriteAic23(L_HEADPHONE_VOLUME,0x0180+volume);
ping_buff_offset++; // Start at location 1 (32-bit r/w from loc. 1, then 0)
pong_buff_offset++; // Start at location 1 (32-bit r/w from loc. 1, then 0)
//init_mcbsp_spi(); // Initialize McBSP-B as SPI Control
out1_offset++; // Start at location 1 (32-bit r/w from loc. 1, then 0)
out2_offset++; // Start at location 1 (32-bit r/w from loc. 1, then 0)
/* Call function to effect transfer */
taskFxn();
while(1)
{
for(i=0;i<64;i++)
{
noise[i] =in_1[i];
noise[i+64] =in_2[i];
error[i] =in_1[i+64];
error[i+64] =in_2[i+64];
}
for(i=0;i<128;i++)
{
if(i<LMS_M)
{
for(j=0;j<=i;j++)
{
lms_x[j] =noise[i-j];
lms_error[j]=error[i-j];
}
}
else
{
for(j=0;j<LMS_M;j++)
{
lms_x[j] = noise[i-j];
lms_error[j]=error[i-j];
}
}
lms_param_in.d = noise[i];//signal_noise[i];
lms_param_in.error = &lms_error[0];
lms_param_in.x_ptr = &lms_x[0];
lms_param_in.length_x = LMS_M;
LMS_Gradient_Instantaneous_Estimates(&lms_param_in, &lms_param_out); //运行瞬时梯度估计LMS算法 耗时514个时钟周期
out_y[i] =lms_param_out.y;
}
for(i=0;i<64;i++)
{
out_1[i]=out_y[i]; //输出左通道
out_1[i+64]=out_y[i]; //输出右通道
out_2[i]=out_y[i+64]; //输出左通道
out_2[i+64]=out_y[i+64];//输出右通道
}
}
}
void taskFxn(void)
{
Uint16 srcAddrHi, srcAddrLo;
Uint16 dstAddrHi, dstAddrLo;
//Uint16 i;
/* for(i=0;i<N;i++)
{
pingrcv[i] = 0;
pongrcv[i] = 0;
pingxmt[i] = 0;
pongxmt[i] = 0;
}*/
/* By default, the TMS320C55xx compiler assigns all data symbols word */
/* addresses. The DMA however, expects all addresses to be byte */
/* addresses. Therefore, we must shift the address by 2 in order to */
/* change the word address to a byte address for the DMA transfer. */
srcAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR(DRR10))) >> 15) & 0xFFFFu;
srcAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR(DRR10))) << 1) & 0xFFFFu;
//srcAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR_H(hMcbsp,DRR1))) >> 15) & 0xFFFFu;
//srcAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR_H(hMcbsp,DRR1))) << 1) & 0xFFFFu;
dstAddrHi = (Uint16)(((Uint32)(&in_1[0])) >> 15) & 0xFFFFu;
dstAddrLo = (Uint16)(((Uint32)(&in_1[0])) << 1) & 0xFFFFu;
dmaRcvConfig.dmacssal = (DMA_AdrPtr)srcAddrLo;
dmaRcvConfig.dmacssau = srcAddrHi;
dmaRcvConfig.dmacdsal = (DMA_AdrPtr)dstAddrLo;
dmaRcvConfig.dmacdsau = dstAddrHi;
srcAddrHi = (Uint16)(((Uint32)(&out_1[0])) >> 15) & 0xFFFFu;
srcAddrLo = (Uint16)(((Uint32)(&out_1[0])) << 1) & 0xFFFFu;
dstAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR(DXR10))) >> 15) & 0xFFFFu;
dstAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR(DXR10))) << 1) & 0xFFFFu;
//dstAddrHi = (Uint16)(((Uint32)(MCBSP_ADDR_H(hMcbsp,DXR1))) >> 15) & 0xFFFFu;
//dstAddrLo = (Uint16)(((Uint32)(MCBSP_ADDR_H(hMcbsp,DXR1))) << 1) & 0xFFFFu;
dmaXmtConfig.dmacssal = (DMA_AdrPtr)srcAddrLo;
dmaXmtConfig.dmacssau = srcAddrHi;
dmaXmtConfig.dmacdsal = (DMA_AdrPtr)dstAddrLo;
dmaXmtConfig.dmacdsau = dstAddrHi;
/* Open MCBSP Port 1 and set registers to their power on defaults */
hMcbsp = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);
/* Open DMA channels 4 & 5 and set regs to power on defaults */
hDmaRcv = DMA_open(DMA_CHA4,DMA_OPEN_RESET);
hDmaXmt = DMA_open(DMA_CHA5,DMA_OPEN_RESET);
/* Get interrupt event associated with DMA receive and transmit */
xmtEventId = DMA_getEventId(hDmaXmt);
rcvEventId = DMA_getEventId(hDmaRcv);
/* Temporarily disable interrupts and clear any pending */
/* interrupts for MCBSP transmit */
old_intm = IRQ_globalDisable();
/* Clear any pending interrupts for DMA channels */
IRQ_clear(xmtEventId);
IRQ_clear(rcvEventId);
/* Enable DMA interrupt in IER register */
IRQ_enable(xmtEventId);
IRQ_enable(rcvEventId);
/* Set Start Of Interrupt Vector Table */
IRQ_setVecs(0x10000);
/* Place DMA interrupt service addresses at associate vector */
IRQ_plug(xmtEventId,&dmaXmtIsr);
IRQ_plug(rcvEventId,&dmaRcvIsr);
/* Write values from configuration structure to MCBSP control regs */
MCBSP_config(hMcbsp, &ConfigLoopBack16);
/* Write values from configuration structure to DMA control regs */
DMA_config(hDmaRcv,&dmaRcvConfig);
DMA_config(hDmaXmt,&dmaXmtConfig);
xfreebuf = xpongbuf;
rfreebuf = rpongbuf;
/* Enable all maskable interrupts */
IRQ_globalEnable();
/* Start Sample Rate Generator and Enable Frame Sync */
MCBSP_start(hMcbsp,
MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC,
0x300u);
//DMA_FSETH (hDmaRcv, DMACCR, ENDPROG, 1);
//DMA_FSETH (hDmaXmt, DMACCR, ENDPROG, 1);
/* Enable DMA */
DMA_start(hDmaRcv);
DMA_start(hDmaXmt);
/* Take MCBSP transmit and receive out of reset */
MCBSP_start(hMcbsp,
MCBSP_XMIT_START | MCBSP_RCV_START,
0u);
while(DMA_FGETH(hDmaRcv, DMACCR, ENDPROG));
while(1)
{
;}
/*dstAddrHi = (Uint16)(((Uint32)(&in_2[0])) >> 15) & 0xFFFFu;
dstAddrLo = (Uint16)(((Uint32)(&in_2[0])) << 1) & 0xFFFFu;
dmaRcvConfig.dmacdsal = (DMA_AdrPtr)dstAddrLo;
dmaRcvConfig.dmacdsau = dstAddrHi;
srcAddrHi = (Uint16)(((Uint32)(&out_2[0])) >> 15) & 0xFFFFu;
srcAddrLo = (Uint16)(((Uint32)(&out_2[0])) << 1) & 0xFFFFu;
dmaXmtConfig.dmacssal = (DMA_AdrPtr)srcAddrLo;
dmaXmtConfig.dmacssau = srcAddrHi;
DMA_FSETH(hDmaRcv, DMACCR, ENDPROG,1);
DMA_FSETH(hDmaXmt, DMACCR, ENDPROG,1);*/
}
interrupt void dmaXmtIsr(void)
{
//static int * ptr;
//unsigned int ptraddrhi, ptraddrlow;
Uint16 srcAddrHi, srcAddrLo;
//Uint16 dstAddrHi, dstAddrLo;
DMA_FSETH(hDmaXmt,DMACSR,BLOCK,0);
DMA_FSETH(hDmaXmt,DMACSR,FRAME,0);
/*RecvComplete=1; //!!!!!!!!!
dmaXmtIsr_count++; //!!!!!!!!!!!
if(xfreebuf == xpingbuf)
{
xfreebuf = xpongbuf;
ptr = pongxmt;
}
else
{
xfreebuf = xpingbuf;
ptr = pingxmt;
}
while(DMA_FGETH(hDmaXmt, DMACCR, ENDPROG));
//修改DMA地址
ptraddrhi = (unsigned int)(((unsigned long)(ptr)) >> 15) & 0xFFFFu;
//因为DMA都使用字节地址，所以必须左移一位
ptraddrlow= (unsigned int)(((unsigned long)(ptr)) << 1) & 0xFFFFu;
//dmaXmtConfig.dmacssal = (DMA_AdrPtr)ptraddrlow;//这个地方改了一下，请注意
//dmaXmtConfig.dmacssau = ptraddrhi;
DMA_RSETH(hDmaXmt, DMACSSAU, ptraddrhi);
DMA_RSETH(hDmaXmt, DMACSSAL, ptraddrlow);
DMA_FSETH(hDmaXmt, DMACCR, ENDPROG,1);*/
if(PingPong==PING)
{
srcAddrHi = (Uint16)(((Uint32)(&out_2[0])) >> 15) & 0xFFFFu;
srcAddrLo = (Uint16)(((Uint32)(&out_2[0])) << 1) & 0xFFFFu;
dmaXmtConfig.dmacssal = (DMA_AdrPtr)srcAddrLo;
dmaXmtConfig.dmacssau = srcAddrHi;
PingPong=PONG;
DMA_FSETH(hDmaXmt, DMACCR, ENDPROG,1);
}
else
{
srcAddrHi = (Uint16)(((Uint32)(&out_1[0])) >> 15) & 0xFFFFu;
srcAddrLo = (Uint16)(((Uint32)(&out_1[0])) << 1) & 0xFFFFu;
dmaXmtConfig.dmacssal = (DMA_AdrPtr)srcAddrLo;
dmaXmtConfig.dmacssau = srcAddrHi;
PingPong=PING;
DMA_FSETH(hDmaXmt, DMACCR, ENDPROG,1);
}
DMA_RSETH(hDmaXmt, DMACSSAU, srcAddrHi);
DMA_RSETH(hDmaXmt, DMACSSAL, srcAddrLo);
DMA_start(hDmaXmt);
}
interrupt void dmaRcvIsr(void)
{
/*unsigned int ptraddrhi, ptraddrlow;
DMA_FSETH(hDmaRcv,DMACSR,BLOCK,0);
//RecvComplete=0;
dmaRcvIsr_count++;
if(rfreebuf == rpingbuf)
{
rfreebuf = rpongbuf;
ptr = pongrcv;
}
else
{
rfreebuf = rpingbuf;
ptr = pingrcv;
}
while(DMA_FGETH(hDmaRcv, DMACCR, ENDPROG));
//修改DMA地址
ptraddrhi = (unsigned int)(((unsigned long)(ptr)) >> 15) & 0xFFFFu;
//因为DMA都使用字节地址，所以必须左移一位
ptraddrlow= (unsigned int)(((unsigned long)(ptr)) << 1) & 0xFFFFu;
//dmaRcvConfig.dmacdsal = (DMA_AdrPtr)ptraddrlow;
//dmaRcvConfig.dmacdsau = ptraddrhi;
DMA_RSETH(hDmaRcv, DMACSSAU, ptraddrhi);
DMA_RSETH(hDmaRcv, DMACSSAL, ptraddrlow);
DMA_FSETH(hDmaRcv, DMACCR, ENDPROG,1);*/
//Uint16 srcAddrHi, srcAddrLo;
Uint16 dstAddrHi, dstAddrLo;
DMA_FSETH(hDmaRcv,DMACSR,BLOCK,0);
DMA_FSETH(hDmaRcv,DMACSR,FRAME,0);
if(PingPong==PING)
{
dstAddrHi = (Uint16)(((Uint32)(&in_2[0])) >> 15) & 0xFFFFu;
dstAddrLo = (Uint16)(((Uint32)(&in_2[0])) << 1) & 0xFFFFu;
dmaRcvConfig.dmacssal = (DMA_AdrPtr)dstAddrLo;
dmaRcvConfig.dmacssau = dstAddrHi;
PingPong=PONG;
DMA_FSETH(hDmaXmt, DMACCR, ENDPROG,1);
}
else
{
dstAddrHi = (Uint16)(((Uint32)(&in_1[0])) >> 15) & 0xFFFFu;
dstAddrLo = (Uint16)(((Uint32)(&in_1[0])) << 1) & 0xFFFFu;
dmaRcvConfig.dmacssal = (DMA_AdrPtr)dstAddrLo;
dmaRcvConfig.dmacssau = dstAddrHi;
PingPong=PING;
DMA_FSETH(hDmaXmt, DMACCR, ENDPROG,1);
}
DMA_RSETH(hDmaRcv, DMACSSAU, dstAddrHi);
DMA_RSETH(hDmaRcv, DMACSSAL, dstAddrLo);
DMA_start(hDmaRcv);
}
void WriteAic23(Uint16 addr,Uint16 dat)
{
Uint16 i,Temp;
Temp = addr<<9;
dat = dat | Temp;
//CS=0;
tAicRegs = tAicRegs & ClrAICCS;
SysReg = tAicRegs;
delay(200); // DELAY_US(200);
for(i=0;i<16;i++)
{
//SCLK=0;
tAicRegs = tAicRegs & ClrSCLK;
SysReg = tAicRegs;
delay(200); // DELAY_US(200);
Temp = dat<<i;
Temp = Temp & 0x8000;
if (Temp)
{
tAicRegs = tAicRegs | SetSIDIN;
SysReg = tAicRegs;
}
else{
tAicRegs = tAicRegs & ClrSIDIN;
SysReg = tAicRegs;
}
delay(100); // DELAY_US(100);
tAicRegs = tAicRegs | SetSCLK; //SCLK=1;
SysReg = tAicRegs;
delay(100); // DELAY_US(100);
}
//SCLK=0;
tAicRegs = tAicRegs & ClrSCLK;
SysReg = tAicRegs;
delay(200); //DELAY_US(200);
//CS=1;
tAicRegs = tAicRegs | SetAICCS;
SysReg = tAicRegs;
delay(1000); // DELAY_US(1000);
}
void InitAic23()
{
WriteAic23(RESET,0);
WriteAic23(D_INTERFACE_ACT,0x001);
WriteAic23(POWER_CON,0);
WriteAic23(SAMPLE_RATE,0x022); //44.1k
// WriteAic23(SAMPLE_RATE,0x062); //22.05k
// write_AIC23(SAMPLE_RATE,0x02e); //8.021k
WriteAic23(L_LINE_VOLUME,0x0117);
WriteAic23(R_LINE_VOLUME,0x0117);
volume=108;
WriteAic23(L_HEADPHONE_VOLUME,0x0180+volume);
WriteAic23(R_HEADPHONE_VOLUME,0x0180+volume);
// write_AIC23(A_AUDIO_PATH,0x009); //bypass DAC OFF
// write_AIC23(A_AUDIO_PATH,0x014); //MIC ADC DAC ON 0DB
// write_AIC23(A_AUDIO_PATH,0x1fc); //bypass MIC ADC DAC ON 0DB sidetone
WriteAic23(A_AUDIO_PATH,0x07d); //bypass MIC ADC DAC ON 20DB sidetone(-6db)
// write_AIC23(A_AUDIO_PATH,0x011); //LINE ADC DAC ON
WriteAic23(D_AUDIO_PATH,0x04);
WriteAic23(D_AUDIO_INTERFACE,0x043); //master dsp mode 16BIT
}
void delay(Uint32 k)
{
while(k--);
}
|
|
楼主
标题置顶
标题高亮
