如何使用xilinx的MIG

只看该作者 · 2011-11-28 16:00

各位老大，本人使用spatan6的开发板做DDRII的验证，但是生成MIG ip之后，把xco文件加入project，自己写代码例化后，上板子没任何反应，监控后发现c3_clk0没有，可以确认sysclk肯定有，但不是差分的clk，clk配置成single-ended，代码如下

ddr_ip my_ddr_inst(
.mcb3_dram_dq(DDR_DQ),
.mcb3_dram_a(DDR_ADDR),
.mcb3_dram_ba(DDR_BA),
.mcb3_dram_ras_n(DDR_RAS_N),
.mcb3_dram_cas_n(DDR_CAS_N),
.mcb3_dram_we_n(DDR_WE_N),
.mcb3_dram_odt(DDR_ODT),
.mcb3_dram_cke(DDR_CKE),
.mcb3_dram_dm(DDR_LDM),
.mcb3_dram_udqs(DDR_UDQS_P),
.mcb3_dram_udqs_n(DDR_UDQS_N),
.mcb3_rzq(DDR_RZQ),
.mcb3_zio(DDR_ZIO),
.mcb3_dram_udm(DDR_UDM),
.c3_sys_clk(clk100),
.c3_sys_rst_n(RESET_N),
.c3_calib_done(cal_done),
.c3_clk0(user_clk),
.c3_rst0(rst0),
.mcb3_dram_dqs(DDR_LDQS_P),
.mcb3_dram_dqs_n(DDR_LDQS_N),
.mcb3_dram_ck(DDR_CLK),
.mcb3_dram_ck_n(DDR_CLK_N),
.c3_p0_cmd_clk(user_clk),
.c3_p0_cmd_en(user_cmd_en),
.c3_p0_cmd_instr(user_cmd_instr),
.c3_p0_cmd_bl(user_cmd_bl),
.c3_p0_cmd_byte_addr(user_cmd_byte_addr),

.c3_p0_cmd_empty(user_cmd_empty),
.c3_p0_cmd_full(cmd_full),

.c3_p0_wr_clk(user_clk),
.c3_p0_wr_en(user_wr_en),
.c3_p0_wr_mask(user_wr_mask),
.c3_p0_wr_data(user_wr_data),

.c3_p0_wr_full(wr_full),
.c3_p0_wr_empty(user_wr_empty),
.c3_p0_wr_count(wr_count),
.c3_p0_wr_underrun(wr_underrun),
.c3_p0_wr_error(wr_error),

.c3_p0_rd_clk(user_clk),
.c3_p0_rd_en(user_rd_en),

.c3_p0_rd_data(rd_data),
.c3_p0_rd_full(rd_full),
.c3_p0_rd_empty(rd_empty),
.c3_p0_rd_count(rd_count),
.c3_p0_rd_overflow(rd_overflow),
.c3_p0_rd_error(rd_error)
);

大写的信号都是板子的i/o口的信号