FPGA状态机实现单一功能模十计数器

只看该作者 · 2011-12-9 21:50

本帖最后由 269152492 于 2011-12-9 21:53 编辑

//Data：2011-11月
//功能：状态机实现单一功能模十计数器
module Fsm_Counter(counter,Fillout,clk);
output [3:0] counter;
output Fillout;
reg[3:0]counter;
reg Fillout;
input clk;
parameter State0=4'b0000,
   State1=4'b0001,
   State2=4'b0010,
   State3=4'b0011,
   State4=4'b0100,
   State5=4'b0101,
   State6=4'b0110,
   State7=4'b0111,
   State8=4'b1000,
   State9=4'b1001;
reg[3:0] next_State;
[email=always@(posedge]always@(posedge[/email] clk)
begin
  case(next_State)
State0:next_State<=State1;
State1:next_State<=State2;
State2:next_State<=State3;
State3:next_State<=State4;
State4:next_State<=State5;
State5:next_State<=State6;
State6:next_State<=State7;
State7:next_State<=State8;
State8:next_State<=State9;
State9:next_State<=State0;
default:next_State<=State0;
  endcase
end
[email=always@(next_State]always@(next_State[/email])
begin
  case(next_State)
State0:counter<=State0;
State1:counter<=State1;
State2:counter<=State2;
State3:counter<=State3;
State4:counter<=State4;
State5:counter<=State5;
State6:counter<=State6;
State7:counter<=State7;
State8:counter<=State8;
State9:begin
   counter<=State9;
   Fillout<=1'b1;
   end
default:counter<=State0;
  endcase
end
endmodule