第一种：利用Case_When
process (sel, d)
begin
case sel is
when "00" =>mux_out <= d(0);
when "01" =>mux_out <= d(1);
when "10" =>mux_out <= d(2);
when "11" => mux_out<= d(3);
when others => mux_out <= 'Z';
end case;
end process;
第三种：利用单一when_else
architecture when_else of muxgate is
begin
mux_out <= d(0) when sel = "00" else
d(1) when sel = "01" else
d(2) when sel = "10" else
d(3) when sel= "11" else 'Z';
第四种：利用with_select
architecture with_select of muxgate is
begin
with sel select
mux_out<= d(0) when "00",
d(1) when "01 ",
d(2) when "10",
d(3) when "11",
'Z' when others;
end with_select;
第五种：利用if_then_else
architecture if_then_else of muxgate is
begin
process (sel,d)
begin
if sel = "00" then mux out <= d(0);
elsif sel = "01" then mux_out <= d(1);
elsif sel= "10" then mux_out <= d(2),
elsif sel = "11" then mux_out <= d(3);
else mux_out <='Z';
end if;
end process;
end if_then_else;
给爆个猛的
entity n_to_1_mux_andorbased is
generic(
C_AND_PIPELINE:integer :=1;
C_OR_PIPELINE:integer :=2;
NUM_BIT:integer :=8;
NUM_NPORT:integer :=64
);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
datain : in STD_LOGIC_VECTOR (0 to NUM_BIT*NUM_NPORT-1);
dataout : out STD_LOGIC_VECTOR (0 to NUM_BIT-1);
ch_sel : in STD_LOGIC_VECTOR(0 to NUM_NPORT-1) --left to right sel 0 to n-1
);
编译结果，64路8bit的mux，V5-LX50T-1
Selected Device : 5vlx50tff665-1
Slice Logic Utilization:
Number of Slice Registers: 584 out of 28800 2%
Number of Slice LUTs: 584 out of 28800 2%
Number used as Logic: 584 out of 28800 2%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 584
Number with an unused Flip Flop: 0 out of 584 0%
Number with an unused LUT: 0 out of 584 0%
Number of fully used LUT-FF pairs: 584 out of 584 100%
Number of unique control sets: 73
Timing Summary:
---------------
Speed Grade: -1
Minimum period: 1.885ns (Maximum Frequency: 530.504MHz)
Minimum input arrival time before clock: 0.573ns
Maximum output required time after clock: 0.471ns
Maximum combinational path delay: No path found
Slice Logic Utilization:
Number of Slice Registers: 1160 out of 28800 4%
Number of Slice LUTs: 1184 out of 28800 4%
Number used as Logic: 1184 out of 28800 4%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 1184
Number with an unused Flip Flop: 24 out of 1184 2%
Number with an unused LUT: 0 out of 1184 0%
Number of fully used LUT-FF pairs: 1160 out of 1184 97%
Number of unique control sets: 137
Timing Summary:
---------------
Speed Grade: -1
Minimum period: 2.208ns (Maximum Frequency: 452.899MHz)
Minimum input arrival time before clock: 0.573ns
Maximum output required time after clock: 0.471ns
Maximum combinational path delay: No path found
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