GPIO
The MAX30208 provides access to two GPIO pins which can be used to provide additional functionality. GPIO0 can be configured to output an interrupt while GPIO1 can be configured as an input for a temperature conversion. The interrupt on GPIO0 is triggered based on selectable status bits in the INTERRUPT_ENABLE[0x01] register. By writing to one of the availabe bits in the INTERRUPT_ ENABLE register, the flag for an interrupt is raised if GPIO0_MODE[1:0] in the GPIO_SETUP [0x20] register is set to 11. When GPIO1_MODE[7:0] in the GPIO_SETUP register is set to 11, driving the line low initiates an exter- nal temperature conversion. Table 2 shows a complete list of the functions of the two GPIO Pins.
Table 2. GPIO Mode Functions
Table 3. I2C Slave Address
The state of GPIO pins at each I2C start condition is used to determine the last two bits of the I2C address. This use of the GPIO pins is further detailed below in the I2C Slave Address section.
I2C
I2C Slave Address
I2C Slave Address is 8 bits as shown in Table 3. Bit 0 is 0 for a write operation and 1 for a read operation.
At powerup, GPIO0 and GPIO1 are set to mode 10 as shown in Table 3. The I2C address is determined by the state of these pins. If the mode of either of the GPIO pins is changed to 01 or 11 then those address pins are automatically pulled low internally and can change the I2C address.
I2C/SMBus Compatible Serial Interface
The MAX30208 features an I2C/SMBus-compatible, 2-wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facil- itate communication between the MAX30208 and the master at clock rates up to 400kHz. Figure 3 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the MAX30208 by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) con- dition and a STOP (P) condition. Each word transmitted to the MAX30208 is 8-bits long and is followed by an acknowledge clock pulse. A master reading data from the MAX30208 transmits the proper slave address followed by a series of nine SCL pulses. The MAX30208 transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START (S) or REPEATED START (Sr) condition, a not acknowledge, and a STOP (P) condition. SDA operates as both an input and an open-drain output. A pullup resistor is required on SDA. SCL operates only as an input. A pullup resis- tor is required on SCL if there are multiple masters on
the bus, or if the single master has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX30208 from high voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals.
Detailed I2C Timing Diagram
The detailed timing diagram is shown in Figure 3. Bit Transfer
One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section).
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A mas- ter initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 4). A START condition from the master signals the beginning of a transmission to the MAX30208. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is gen- erated instead of a STOP condition.
Early STOP Conditions
The MAX30208 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition.
Acknowledge Bit
The acknowledge bit (ACK) is a clocked 9th bit that the MAX30208 uses to handshake receipt of each byte of data when in write mode Figure 5. The MAX30208 pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master retries communication. The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the MAX30208 is in read mode. An acknowledge is sent by
the master after each read byte to allow data transfer to continue. A not-acknowledge is sent when the master reads the final byte of data from the MAX30208 followed by a STOP condition.
I2C Write Data Format
A write to the MAX30208 includes transmission of a START condition, the slave address with the R/W bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition. Figure 6 illustrates the proper frame format for writing one byte of data to the MAX30208. Figure 7 illustrates the frame format for writing n-bytes of data to the MAX30208.
The master first sends the slave address with the R/W bit set to 0. This indicates that the master intends to write data to the MAX30208. The MAX30208 acknowledges receipt of the address byte during the master-generated 9th SCL pulse. |
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