一个在用的epwm1的配置，是一个pwm1A跟pwm1B互补的配置。
//-------------------------------------------------------------------------
// Epwm1
//-------------------------------------------------------------------------
UNPROTECT_REGS();
EPwm1Regs.TZCTL.bit.TZA = TZ_NO_CHANGE;
EPwm1Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;
PROTECT_REGS();
//Time-Base Period Register (TBPRD) Field Descriptions
EPwm1Regs.TBPRD = KSwPrdCnst;
EPwm1Regs.CMPA.half.CMPA = (KSwPrdCnst >> 1); // set duty 50% initially
//These bits set time-base counter phase of the selected ePWM relative to the time-base that is
//supplying the synchronization input signal.
// · If TBCTL[PHSEN] = 0, then the synchronization event is ignored and the time-base counter is
// not loaded with the phase.
// · If TBCTL[PHSEN] = 1, then the time-base counter (TBCTR) will be loaded with the phase
// (TBPHS) when a synchronization event occurs. The synchronization event can be initiated by
// the input synchronization signal (EPWMxSYNCI) or by a software forced synchronization.
EPwm1Regs.TBPHS.all = 0;
//Time-Base Counter Register (TBCTR) Field Descriptions
EPwm1Regs.TBCTR = 0;
//Counter Mode
//The time-base counter mode is normally configured once and not changed during normal operation.
//If you change the mode of the counter, the change will take effect at the next TBCLK edge and the
//current counter value shall increment or decrement from the value before the mode change.
//These bits set the time-base counter mode of operation as follows:
// 00 Up-count mode
// 01 Down-count mode
// 10 Up-down-count mode
// 11 Stop-freeze counter operation (default on reset)
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; //Symmetrical mode.
//Counter Register Load From Phase Register Enable
// 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS)
// 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or
// when a software synchronization is forced by the SWFSYNC bit
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; //Mater module.
//Active Period Register Load From Shadow Register Select
// 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter,
// TBCTR, is equal to zero. A write or read to the TBPRD register accesses the shadow register.
// 1 Load the TBPRD register immediately without using a shadow register.
// A write or read to the TBPRD register directly accesses the active register.
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; // Load PRD at zero point.
//Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal.
// 00 EPWMxSYNC:
// 01 CTR = zero: Time-base counter equal to zero (TBCTR = 0x0000)
// 10 CTR = CMPB : Time-base counter equal to counter-compare B (TBCTR = CMPB)
// 11 Disable EPWMxSYNCO signal
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //Sync down-stream module.
//High Speed Time-base Clock Prescale Bits
//These bits determine part of the time-base clock prescale value.
//TBCLK = SYSCLKOUT / (HSPCLKDIV * CLKDIV)
//This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager (EV) peripheral.
// 000 /1
// 001 /2 (default on reset)
// 010 /4
// 011 /6
// 100 /8
// 101 /10
// 110 /12
// 111 /14
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //TbClk = SysClk/2 = 150M /2 = 75M
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2;
//Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during
//emulation events:
// 00 Stop after the next time-base counter increment or decrement
// 01 Stop when counter completes a whole cycle:
// · Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD)
// · Down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000)
// · Up-down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000)
// 1X Free run
EPwm1Regs.TBCTL.bit.FREE_SOFT = 0x03;
//Active Counter-Compare A (CMPA) Load From Shadow Select Mode.
//This bit has no effect in immediate mode (CMPCTL[SHDWAMODE] = 1).
// 00 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
// 01 Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
// 10 Load on either CTR = Zero or CTR = PRD
// 11 Freeze (no loads possible)
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; //To avoid asymmetrical current,just load at zero point.
//Active Counter-Compare B (CMPB) Load From Shadow Select Mode
//This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1).
// 00 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
// 01 Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
// 10 Load on either CTR = Zero or CTR = PRD
// 11 Freeze (no loads possible)
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//Counter-compare A (CMPA) Register Operating Mode
// 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register.
// 1 Immediate mode. Only the active compare register is used. All writes and reads directly
// access the active register for immediate compare action
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
//Counter-compare B (CMPB) Register Operating Mode
// 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register.
// 1 Immediate mode. Only the active compare B register is used. All writes and reads directly
// access the active register for immediate compare action.
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
//Action when the counter equals the active CMPA register and the counter is incrementing.
// 00 Do nothing (action disabled)
// 01 Clear: force EPWMxA output low.
// 10 Set: force EPWMxA output high.
// 11 Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
//Action when the counter equals the active CMPA register and the counter is decrementing.
// 00 Do nothing (action disabled)
// 01 Clear: force EPWMxA output low.
// 10 Set: force EPWMxA output high.
// 11 Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
//Action when the counter equals the active CMPA register and the counter is incrementing.
//00 Do nothing (action disabled)
//01 Clear: force EPWMxB output low.
//10 Set: force EPWMxB output high.
//11 Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.
EPwm1Regs.AQCTLB.bit.CAU = AQ_SET;
//Action when the counter equals the active CMPA register and the counter is decrementing.
// 00 Do nothing (action disabled)
// 01 Clear: force EPWMxB output low.
// 10 Set: force EPWMxB output high.
// 11 Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.
EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;
//Dead-band Output Mode Control
// Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 2-28.
// This allows you to selectively enable or bypass the dead-band generation for the falling-edge
// and rising-edge delay.
// 00 Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA
// and EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper
// submodule.
// In this mode, the POLSEL and IN_MODE bits have no effect.
// 01 Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight
// through to the EPWMxA input of the PWM-chopper submodule.
// The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is
// determined by DBCTL[IN_MODE].
// 10 The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is
// determined by DBCTL[IN_MODE].
// Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight
// through to the EPWMxB input of the PWM-chopper submodule.
// 11 Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge
// delay on output EPWMxB. The input signal for the delay is determined by DBCTL[IN_MODE].
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
//Polarity Select Control
// Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 2-28.
// This allows you to selectively invert one of the delayed signals before it is sent out of the
// dead-band submodule.
// The following descriptions correspond to classical upper/lower switch control as found in one
// leg of a digital motor control inverter.
// These assume that DBCTL[OUT_MODE] = 1,1 and DBCTL[IN_MODE] = 0,0. Other
// enhanced modes are also possible, but not regarded as typical usage modes.
// 00 Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default).
// 01 Active low complementary (ALC) mode. EPWMxA is inverted.
// 10 Active high complementary (AHC). EPWMxB is inverted.
// 11 Active low (AL) mode. Both EPWMxA and EPWMxB are inverted.
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
//Dead Band Input Mode Control
// Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 2-28.
// This allows you to select the input source to the falling-edge and rising-edge delay.
// To produce classical dead-band waveforms the default is EPWMxA In is the source for both
// falling and rising-edge delays.
// 00 EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.
// 01 EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal.
// EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal.
// 10 EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal.
// EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal.
//11 EPWMxB In (from the action-qualifier)
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED;
//
EPwm1Regs.DBFED = TBCLK_MHZ * DBTIME_US;
EPwm1Regs.DBRED = TBCLK_MHZ * DBTIME_US;
// the active register load immediately
EPwm1Regs.AQSFRC.bit.RLDCSF = 3;
//Continuous Software Force on Output A
//In immediate mode, a continuous force takes effect on the next TBCLK edge.
//In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into
//the active register.
// 00 Forcing disabled, i.e., has no effect
// 01 Forces a continuous low on output A
// 10 Forces a continuous high on output A
// 11 Software forcing is disabled and has no effect
EPwm1Regs.AQCSFRC.bit.CSFA = AQ_CLEAR;
//Continuous Software Force on Output B
//In immediate mode, a continuous force takes effect on the next TBCLK edge.
//In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into
//the active register. To configure shadow mode, use AQSFRC[RLDCSF].
// 00 Forcing disabled, i.e., has no effect
// 01 Forces a continuous low on output B
// 10 Forces a continuous high on output B
// 11 Software forcing is disabled and has no effect
EPwm1Regs.AQCSFRC.bit.CSFB = AQ_SET;
//ePWM Interrupt (EPWMx_INT) Selection Options
// 000 Reserved
// 001 Enable event time-base counter equal to zero. (TBCTR = 0x0000)
// 010 Enable event time-base counter equal to period (TBCTR = TBPRD)
// 011 Reserved
// 100 Enable event time-base counter equal to CMPA when the timer is incrementing.
// 101 Enable event time-base counter equal to CMPA when the timer is decrementing.
// 110 Enable event: time-base counter equal to CMPB when the timer is incrementing.
// 111 Enable event: time-base counter equal to CMPB when the timer is decrementing.
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRD;
//Enable ePWM Interrupt (EPWMx_INT) Generation
// 0 Disable EPWMx_INT generation
// 1 Enable EPWMx_INT generation
EPwm1Regs.ETSEL.bit.INTEN = 1;
//ePWM Interrupt (EPWMx_INT) Period Select
// These bits determine how many selected ETSEL[INTSEL] events need to occur before an
// interrupt is generated. To be generated, the interrupt must be enabled (ETSEL[INT] = 1). If
// the interrupt status flag is set from a previous interrupt (ET**[INT] = 1) then no interrupt will
// be generated until the flag is cleared via the ETCLR[INT] bit. This allows for one interrupt to
// be pending while another is still being serviced. Once the interrupt is generated, the
// ETPS[INTCNT] bits will automatically be cleared.
// Writing a INTPRD value that is the same as the current counter value will trigger an interrupt
//if it is enabled and the status flag is clear.
//Writing a INTPRD value that is less than the current counter value will result in an undefined state.
//If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is
//written, the counter is incremented.
// 00 Disable the interrupt event counter. No interrupt will be generated and ETFRC[INT] is ignored.
// 01 Generate an interrupt on the first event INTCNT = 01 (first event)
// 10 Generate interrupt on ETPS[INTCNT] = 1,0 (second event)
// 11 Generate interrupt on ETPS[INTCNT] = 1,1 (third event)
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; |
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