亲，VHDL , 我定义了2个数组， 现在将数组B赋值给数组A,
TYPE DATA_SS IS ARRAY(0 TO 79) OF std_logic_vector(11 downto 0);
signal temp_data : DATA_SS;
TYPE DATA_SSS IS ARRAY(0 TO 9) OF std_logic_vector(11 downto 0);
signal ch1_s : DATA_SSS;
temp_data( 0 to 9) <= ch1_s(0 to 9);
编译时出错，Error (10381): VHDL Type Mismatch error at AA.vhd(329): indexed name returns a value whose type does not match "DATA_SS", the type of the target expression
有好的赋值方法吗？ 单独一个一个的赋值是没有问题的，但太麻烦 |
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