reg clk = 0;
initial begin
forever #5 clk = ~clk;
end
reg RamWea = 0;
reg Rden = 0;
initial begin
#102; RamWea=1;
#2560;RamWea=0;
#1000; Rden = 1;
#655360;Rden = 0;
end
reg [7:0] RamAddra=0;
always [url=home.php?mod=space&uid=72445]@[/url] ( posedge clk )
begin
if( RamWea ) RamAddra <= RamAddra + 1'b1;
else RamAddra <= 8'b0;
end
wire [7:0] RamDina = RamAddra;
reg [7 : 0] RdAddrb = 0;
always @ ( posedge clk )
begin
if( Rden ) RdAddrb <= RdAddrb + 1'b1;
else RdAddrb <= 8'b0;
end
wire [7 : 0] RdDoutb;
blkram_8x256 blkram_8x256 (
.clka (clk), // input wire clka
.wea (RamWea), // input wire [0 : 0] wea
.addra (RamAddra), // input wire [7 : 0] addra
.dina (RamDina), // input wire [7 : 0] dina
.clkb (clk), // input wire clkb
.addrb (RdAddrb), // input wire [7 : 0] addrb
.doutb (RdDoutb) // output wire [7 : 0] doutb
);
integer file_out;
initial
begin
file_out = $fopen("E:\\CANNY\\CANNY\\CANNY.sim\\out_file0.txt");
if (!file_out)
begin
$finish;
end
end
reg RdenD1 = 0;
reg RdenD2 = 0;
always @ (posedge clk)
begin
RdenD1 <= Rden;
RdenD2 <= RdenD1;
end
always @ (posedge clk)
begin
if( RdenD1 )
$fwrite(file_out," %d",RdDoutb) ;//写入文件，在%d前加入一个空格，效果就是，个位数前有3个空格，两位数前两个空格，三位数前1个空格
end
always @ (posedge clk)
begin
if( ~RdenD1 & RdenD2 )
$fclose(file_out);
end
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