加入chipscope就报错，简单看了一下资源应该足够用；搞不懂。芯片是xc6slx25t
错误信息
ERROR:Place:543 - This design does not fit into the number of slices available in this device due to the complexity of
the design and/or constraints.
ERROR:Place:120 - There were not enough sites to place all selected components.
Some of these failures can be circumvented by using an alternate algorithm (though it may take longer run time). If
you would like to enable this algorithm please set the environment variable XIL_PAR_ENABLE_LEGALIZER to 1 and try
again
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
map 报告
Slice Logic Utilization:
Number of Slice Registers: 324 out of 30,064 1%
Number used as Flip Flops: 323
Number used as Latches: 1
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 299 out of 15,032 1%
Number used as logic: 219 out of 15,032 1%
Number using O6 output only: 118
Number using O5 output only: 75
Number using O5 and O6: 26
Number used as ROM: 0
Number used as Memory: 73 out of 3,664 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 73
Number using O6 output only: 71
Number using O5 output only: 1
Number using O5 and O6: 1
Number used exclusively as route-thrus: 7
Number with same-slice register load: 0
Number with same-slice carry load: 7
Number with other load: 0
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 484
Number with an unused Flip Flop: 160 out of 484 33%
Number with an unused LUT: 185 out of 484 38%
Number of fully used LUT-FF pairs: 139 out of 484 28%
Number of unique control sets: 58
Number of slice register sites lost
to control set restrictions: 282 out of 30,064 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 12 out of 190 6%
Number of LOCed IOBs: 12 out of 12 100%
IOB Master Pads: 5
IOB Slave Pads: 5
Specific Feature Utilization:
Number of RAMB16BWERs: 16 out of 52 30%
Number of RAMB8BWERs: 0 out of 104 0%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 272 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 272 0%
Number of OLOGIC2/OSERDES2s: 10 out of 272 3%
Number used as OLOGIC2s: 0
Number used as OSERDES2s: 10
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 160 0%
Number of BUFPLLs: 1 out of 8 12%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 38 0%
Number of GTPA1_DUALs: 0 out of 1 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 2 50%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Number of RPM macros: 9 |
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