**********************************************************************************************************************************************
Well I had this doubt when I was learning Verilog: What is the difference between reg and wire? Well I won't tell stories to explain this, rather I will give you some examples to show the difference.
There is something else about wire which sometimes confuses. wire data types can be used for connecting the output port to the actual driver. Below is the code which when synthesized gives a AND gate as output, as we know a AND gate can drive a load.
view plaincopy to clipboardprint?
module wire_example( a, b, y);
input a, b;
output y;
wire a, b, y;
assign y = a & b;
endmodule
module wire_example( a, b, y);
input a, b;
output y;
wire a, b, y;
assign y = a & b;
endmodule
SYNTHESIS OUTPUT
What this implies is that wire is used for designing combinational logic, as we all know that this kind of logic can not store a value. As you can see from the example above, a wire can be assigned a value by an assign statement. Default data type is wire: this means that if you declare a variable without specifying reg or wire, it will be a 1-bit wide wire.
Now, coming to reg data type, reg can store value and drive strength. Something that we need to know about reg is that it can be used for modeling both combinational and sequential logic. Reg data type can be driven from initial and always block.
Reg data type as Combinational element
view plaincopy to clipboardprint?
module reg_combo_example( a, b, y);
input a, b;
output y;
reg y;
wire a, b;
always @ ( a or b)
begin
y = a & b;
end
endmodule
module reg_combo_example( a, b, y);
input a, b;
output y;
reg y;
wire a, b;
always @ ( a or b)
begin
y = a & b;
end
endmodule
|