又遇到一个问题: ERROR:Place 1012

发表于 2012-1-20 17:59

本帖最后由 nongfuxu 于 2012-1-20 18:00 编辑

重建一次再ＰＲ时，出现如下问题：
ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair.

发表于 2012-1-20 18:02

查网后找到原因：
由于非GCLK脚不具有BUFG，在 PALCE&ROUTE由于为找到IBUFG而出错。

发表于 2012-1-20 18:44

解决方法有二条路径
1)在planahead重要定义CLK IN管脚.
2)若PCB板已经布好,则用以下语句来借道.
< NET "arm_nWE" CLOCK_DEDICATED_ROUTE = FALSE; >

发表于 2012-1-20 18:47

采用第二种方法后,会出现警告,不用管它就行了.
WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component <arm_nWE_BUFGP/BUFG> is placed at site <BUFGMUX7>. The IO component <arm_nWE> is placed at site <P140>. This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <arm_nWE.PAD> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.

发表于 2012-1-20 22:17

:lol
顶一下，

发表于 2012-1-20 22:48

你还没有休息啊!

发表于 2012-1-21 14:15

总结的不错，顶~~~

发表于 2012-1-27 10:11

第二种方式不是解决问题的根本之道。

发表于 2012-1-27 10:12

如果速度不高，第二种方式也可以。

又遇到一个问题: ERROR:Place 1012

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