// USCI_B1 TX buffer ready?
// while (!USCI_B_SPI_getInterruptStatus(USCI_B1_BASE, UCTXIFG));
//Transmit Data to slave
//USCI_B_SPI_transmitData(USCI_B1_BASE, transmitData);
// CPU off, enable interrupts
__bis_SR_register(LPM0_bits + GIE);
//while(1);
}
//******************************************************************************
//
// This is the USCI_B0 interrupt vector service routine.
//
//******************************************************************************
#pragma vector=USCI_B0_VECTOR
__interrupt void USCI_B0_ISR(void)
{
switch(__even_in_range(UCB0IV,4))
{
// Vector 2 - RXIFG
case 2:
while (!USCI_B_SPI_getInterruptStatus(USCI_B0_BASE, UCRXIFG));
receiveData = USCI_B_SPI_receiveData(USCI_B0_BASE);
break;
default: break;
}
}
#pragma vector=USCI_B1_VECTOR
__interrupt void USCI_B1_ISR(void)
{
switch(__even_in_range(UCB1IV,4))
{
// Vector 2 - RXIFG
case 4:
transmitData++;
// Send next value
while (!USCI_B_SPI_getInterruptStatus(USCI_B1_BASE, UCTXIFG));
USCI_B_SPI_transmitData(USCI_B1_BASE, transmitData);
//Delay between transmissions for slave to process information
__delay_cycles(40);
break;
default: break;
}
}