void SYS_Init(void)
{
/* Enable clock source */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Waiting for clock source ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Disable PLL first to avoid unstable when setting PLL */
CLK_DisablePLL();
/* Set PLL frequency */
CLK->PLLCTL = (CLK->PLLCTL & ~(0x000FFFFFUL)) | 0x0000C25EUL;
/* Waiting for PLL ready */
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
/* If the defines do not exist in your project, please refer to the related clk.h in the Header folder appended to the tool package. */
/* Set HCLK clock */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1));
/* Set PCLK-related clock */
CLK->PCLKDIV = (CLK_PCLKDIV_APB0DIV_DIV1 | CLK_PCLKDIV_APB1DIV_DIV1);
/* Enable IP clock */
CLK_EnableModuleClock(PWM1_MODULE);
CLK_EnableModuleClock(TMR0_MODULE);
CLK_EnableModuleClock(TMR1_MODULE);
CLK_EnableModuleClock(TMR2_MODULE);
CLK_EnableModuleClock(TMR3_MODULE);
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(UART1_MODULE);
CLK_EnableModuleClock(UART2_MODULE);
/* Set IP clock */
CLK_SetModuleClock(PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, MODULE_NoMsk);
CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, MODULE_NoMsk);
CLK_SetModuleClock(TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, MODULE_NoMsk);
CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_PCLK1, MODULE_NoMsk);
CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_PCLK1, MODULE_NoMsk);
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART0SEL_PCLK0, CLK_CLKDIV0_UART0(1));
CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UART1SEL_PCLK1, CLK_CLKDIV0_UART1(1));
CLK_SetModuleClock(UART2_MODULE, CLK_CLKSEL3_UART2SEL_PCLK0, CLK_CLKDIV4_UART2(1));
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
SystemCoreClockUpdate();
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