module my_GP(
Input,
Pulse,
clk_in,
Fet_Drive1,
Fet_Drive2,
Fet_Drive3,
Fet_Drive4
);
input [2:0] Input; //输入
input Pulse; //输入
input clk_in;
output Fet_Drive1; //输出
output Fet_Drive2;
output Fet_Drive3;
output Fet_Drive4;
reg Fet_Drive1;
reg Fet_Drive2;
reg Fet_Drive3;
reg Fet_Drive4;
//always #100 clk = (~clk);
always @( posedge clk_in )
begin
if(Pulse)
begin
Fet_Drive1 = 1;
Fet_Drive2 = 1;
Fet_Drive3 = 1;
Fet_Drive4 = 1;
end
else
case(Input)
3'b100: Fet_Drive1 = 0;
3'b101: Fet_Drive2 = Fet_Drive1; <---- 改成非阻塞赋值就出错
3'b110: Fet_Drive3 = Fet_Drive2; <---- 改成非阻塞赋值就出错
3'b111: Fet_Drive4 = Fet_Drive3; <---- 改成非阻塞赋值就出错
endcase
end
endmodule |
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