使用NUC120RD2DN，無法成功將CPUCLK從外部24MHZ XTAL，經PLL倍頻為48MH

1万 · 2021-7-13 09:20

程式設定如下，但CPUCLK一直維持在24MHZ，PLL沒有倍頻輸出

main (void)

{

uint32_t delayCnt;

UNLOCKREG();

SYSCLK->PWRCON.XTL12M_EN = 1; //  24MHZ External X'TAL

SYSCLK->PWRCON.OSC22M_EN = 1;

SYSCLK->PWRCON.OSC10K_EN = 1;

SYSCLK->PWRCON.XTL32K_EN = 1;

for (delayCnt=0;delayCnt<100000;delayCnt++); // Delay for clock stable



SYSCLK->CLKSEL0.HCLK_S = 0x010;       //  HCLK clock source = PLL clock

SYSCLK->PLLCON.PLL_SRC = 0;

SYSCLK->PLLCON.OE = 0;

SYSCLK->PLLCON.BP = 0;

SYSCLK->PLLCON.PD = 0;

SYSCLK->PLLCON.OUT_DV = 3; // NO = 4

SYSCLK->PLLCON.IN_DV = 1; // NR = 3

SYSCLK->PLLCON.FB_DV = 22; // NF = 24

// PLLFOUT = FIN * NF/NR * 1/NO

//    = 24MHZ * 24/3 * 1/4 = 48MHZ

LOCKREG();

只看该作者 · 2021-7-14 09:04

#include "NUC100Series.h"
#define __HXT (24000000UL) /*!< High Speed External Crystal Clock Frequency */

/*
* @brief This function updates clock registers to fulfil the configuration
* @param None
* @return None
*/
void SYS_Init()
{

/* Unlock protected registers */
SYS_UnlockReg();

/* Enable clock source */
CLK_EnableXtalRC(CLK_PWRCON_OSC10K_EN_Msk|CLK_PWRCON_OSC22M_EN_Msk|CLK_PWRCON_XTL32K_EN_Msk|CLK_PWRCON_XTL12M_EN_Msk);

/* Waiting for clock source ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC10K_STB_Msk|CLK_CLKSTATUS_OSC22M_STB_Msk|CLK_CLKSTATUS_XTL32K_STB_Msk|CLK_CLKSTATUS_XTL12M_STB_Msk);

/* Disable PLL first to avoid unstable when setting PLL */
CLK_DisablePLL();

/* Set PLL frequency */
CLK->PLLCON = (CLK->PLLCON & ~(0x000FFFFFul)) | 0x0000C00Eul;

/* Waiting for PLL ready */
CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);

/* If the defines do not exist in your project, please refer to the related clk.h in the Header folder appended to the tool package. */
/* Set HCLK clock */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(1));

/* Enable IP clock */
CLK_EnableModuleClock(ISP_MODULE);
CLK_EnableModuleClock(WDT_MODULE);
CLK_EnableModuleClock(WWDT_MODULE);

/* Set IP clock */
CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDT_S_LIRC, MODULE_NoMsk);
CLK_SetModuleClock(WWDT_MODULE, CLK_CLKSEL2_WWDT_S_HCLK_DIV2048, MODULE_NoMsk);

/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
SystemCoreClockUpdate();

/* Lock protected registers */
SYS_LockReg();

return;
}

使用NUC120RD2DN，無法成功將CPUCLK從外部24MHZ XTAL，經PLL倍頻為48MH

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