the clock controller generates all clocks for vedio, audio, cpu, amba and all engine modules, nuc970 include two PLL Modules;
the clock souce for each module come from the PLL, or from external crystal input directly.
for each clock there is bit on the CLKEN register to control the clock ON or OFF individually (手动. 人工),
and the divider setting is on the CLK_DIVCTL register, the register can also be used to control the clock
enable or disable for power control.
{CLK_XXXEN}
{CLK_XXXDIVCTL}
-------------------------------------------------------------------------------------------------------
PLL (up to 500MHZ) ----> high performance system operation;
12MHZ ex-crystal ----> precise(精准的) timing operation;
32.768KHZ ex-crystal ----> RTC function and low speed clock source;
-------------------------------------------------------------------------------------------------------
=======================================================================================================
CLK_BA = 0xB000_0200
=======================================================================================================
[CLK_PMCOM] Power Management Control Register {
[
The chip clock source is from an external crystal. The crystal oscillator can be control on/off by the
register XTAL_EN. when turn off the crystal, the chip into power down state, to avoid outputting an unstable clock to system,
clock controller implements(实现, 配置) a pre-scalar counter. After the clock counter count pre-scalar x 256 crystal cycle, the clock
controller starts to output the clock to system.
]
[
CLK_PMCOM = CLK_BA + 0x000
[0] XTAL_EN {
= 0, crystal off (Power-down mode);
= 1, crystal on (Normal operating mode);
}
[1] XIN_CTL {
= 0, Disable the pre-scalar, assume the crystal is stable;
= 1, Enable the pre-scalar counter;
}
[4] SEN_OFF_ST {
# Sensor Clock level on Clock Off State
= 0, sensor clock keep on low level;
= 1, sensor clock keep on high level;
}
[8:23] PRESCALE {
# Pre-scalar Counter x 256 .....
}
]
}
[CLK_HCLKEN] AHB Devices Clock Enable Control Register {
[
AHB Devices Clock Enable Control Register.
]
[
CLK_HCLKEN = CLK_BA + 0x010
[0] CPU {
# ARM926EJ-s CPU Clock Enable.
= 0, ARM926EJ-s clock disable;
= 1, ARM926EJ-s clock enable;
}
[1] HCLK {
# Internal AHB Bus Clock Enable.
= 0, Internal AHB bus clock disable;
= 1, Internal AHB bus clock enable;
}
[2] HCLK1 {
# Internal AHB-1 Bus Clock Enable.
= 0, Internal AHB-1 bus clock disable;
= 1, Internal AHB-1 bus clock enable;
}
[3] HCLK3 {
# Internal AHB-3 Bus Clock Enable.
= 0, Internal AHB-3 bus clock disable;
= 1, Internal AHB-3 bus clock enable;
}
[4] HCLK4 {
# Internal AHB-4 Bus Clock Enable.
= 0, Internal AHB-4 bus clock disable;
= 1, Internal AHB-4 bus clock enable;
}
[5] PCLK {
# Interal APB Bus Clock Enable;
= 0, Internal APB bus clock disable;
= 1, Internal APB bus clock enable;
}
[6] Reserved {
.........
}
[7] TIC {
# TIC Clock Enable.
= 0, TIC clock disable;
= 1, TIC clock enable;
}
[8] SRAM {
# SRAM Controller Clock Enable;
= 0, SRAM controller clock disable;
= 1, SRAM controller clock enable;
}
[9] EBI {
# EBI Controller Clock Enable.
= 0, EBI controller clock disable;
= 1, EBI controller clock enable;
}
[10] DDR {
# DDR Clock Enable;
= 0, DDR clock disable;
= 1, DDR clock enable;
}
[11] Reserved {
...........
}
[12] GDMA {
# GDMA Clock Enable;
= 0, GDMA clock disable;
= 1, GDMA clock enable;
}
[13:14] Reserved {
...........
}
[15] CKO {
# Reference Clock Output Enable;
= 0, Reference clock output disable;
= 1, Reference clock output enable;
}
[16] EMAC0 {
# Ethernet MAC Controller 0 Clock Enable;
= 0, Ethernet MAC controller 0 clock disable;
= 1, Ethernet MAC controller 0 clock enable;
}
[17] EMAC1 {
# Ethernet MAC Controller 1 Clock Enable;
= 0, Ethernet MAC controller 1 clock disable;
= 1, Ethernet MAC controller 1 clock enable;
}
[18] USBH {
# USB Host Controller Clock Enable;
= 0, USB host controller clock disable;
= 1, USB host controller clock enable;
}
[19] USBD {
# USB Device Controller Clock Enable;
= 0, USB device controller clock disable;
= 1, USB device controller clock enable;
}
[20] FMI {
# FMI Controller Clock Enable;
= 0, FMI controller clock disable;
= 1, FMI controller clock enable;
}
[21] NAND {
# NAND Engine Clock Enable;
= 0, NAND Engine clock disable;
= 1, NAND Engine clock enable;
}
[22] eMMC {
# eMMC Engine Clock Enable;
= 0, eMMC Engine clock disable;
= 1, eMMC Engine clock enable;
}
[23] CRYPTO {
# Crypto Engine Clock Enable;
= 0, Crypto engine clock disable;
= 1, Crypto engine clock enable;
}
[24] I2S {
# Audio Controller Clock Enable;
= 0, Audio controller clock disable;
= 1, Audio controller clock enable;
}
[25] LCD {
# LCD Display Controller Clock Enable;
= 0, LCD display controller clock disable;
= 1, LCD display controller clock enable;
}
[26] CAP {
# CMOS Sensor Interface Controller Clock Enable;
= 0, CMOS sensor interface controller clock disable;
= 1, CMOS sensor interface controller clock enable;
}
[27] SENSOR {
# CMOS Sensor Reference Clock Output Enable;
= 0, CMOS sensor reference clock output disable;
= 1, CMOS sensor reference clock output enable;
}
[28] GE2D {
# 2G Graphic Engine Clock Enable;
= 0, 2D graphic engine clock disable;
= 1, 2D graphic engine clock enable;
}
[29] JPEG {
# JPEG Codec Clock Enable;
= 0, JPEG codec clock disable;
= 1, JPEG codec clock enable;
}
[30] SDH {
# SD Card Controller Clock Enable;
= 0, SD card controller clock disable;
= 1, SD card controller clock enable;
}
[31] Reserved {
............
}
]
}
CLK_PCLKEN0 {
[0] WDT
[1] WWDT
[2] RTC
[3] GPIO
[4] ETIMER0
[5] ETIMER1
[6] ETIMER2
[7] ETIMER3
[8] TIMER0
[9] TIMER1
[10] TIMER2
[11] TIMER3
[12] TIMER4
[13:15] Reserved
[16] UART0
[17] UART1
[18] UART2
[19] UART3
[20] UART4
[21] UART5
[22] UART6
[23] UART7
[24] UART8
[25] UART9
[26] UART10
[27:32] Reserved
}
CLK_PCLKEN1 {
[0] I2C0
[1] I2C1
[2:3] Reserved
[4] SPI0
[5] SPI1
[6:7] Reserved
[8] CAN0
[9] C
}
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