module bx (
input clk,
input rst_n,
input laser_tx_en,
input [24:0] pwm_width,
input [24:0] pwm_cycle,
input [5:0] laser_tx_num,
output laser_on,
output frame_sync,
output laser_tx_done
);
reg [24 : 0] pwm_cnt;
reg laser_on_i;
reg [5:0] num_cnt;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
pwm_cnt <= 25'd0;
end
else if (laser_tx_en) begin
if (pwm_cnt == pwm_cycle) begin
pwm_cnt <= 25'd0;
end
else
pwm_cnt <= pwm_cnt + 25'd1;
end
else
pwm_cnt <= 25'd0;
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
laser_on_i <= 1'd0;
end
else if (laser_tx_en) begin
case (num_cnt > laser_tx_num)
1'b1: laser_on_i <= 1'd0;
1'b0:if (pwm_cnt <= pwm_width) begin
laser_on_i <= 1'd1;
end
else if (pwm_cnt >= pwm_width) begin
laser_on_i <= 1'd0;
end
else
laser_on_i <= laser_on_i;
default: laser_on_i <= 1'd0;
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
num_cnt <= 6'd0;
end
else if (pwm_cnt == pwm_cycle)begin
num_cnt <= num_cnt + 6'd1;
end
else if (num_cnt > laser_tx_num) begin
num_cnt <= 6'd0;
end
end
assign laser_on = laser_on_i;
assign frame_sync = ((pwm_cnt == 1) & laser_on_i) ? 1'd1 : 1'd0;
assign laser_tx_done = (num_cnt > laser_tx_num) ? 1'd1 : 1'd0;
endmodule
控制脉冲与发射次数,达到一般的通用水准。
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