signal lcx1:STD_LOGIC;
signal lcx2:STD_LOGIC;
process(clk,A,B)
begin
lcx1<=A;
lcx2<=B;
if lcx1='0' and A='1'then
C<-='1';
end if;
if lcx2='0' and B='1'then
C<-='0';
end if;
END PROCESS;
signal lcx1:STD_LOGIC;
signal lcx2:STD_LOGIC;
process(clk,A,B)
begin
if clk'event and clk='1'then
lcx1<=A;
lcx2<=B;
if lcx1='0' and A='1'then
C<-='1';
end if;
if lcx2='0' and B='1'then
C<-='0';
end if;
end if;
END PROCESS;
刚才又尝试用枚举量：
type state_type is (s0, s1);
signal stt: state_type;
case stt is
when s0 =>
if (rising_edge(A))
c<='1';
stt <= s1;
end if;
when s1 =>
if (rising_edge(B))
c<='0';
stt <= s0;
end if;
end case;
可以用很简单的VHDL语言就设计好了，以下是程序：
signal D : STD_LOGIC;
D <= A + B;
process(D)
begin
if D'event and D='1'then
if A = '1' then
C <= '1';
elsif B = '1' then
C <= '0';
end if;
END PROCESS;
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