[ZT]FPGA design from scratch

只看该作者 · 2007-9-5 11:56

PS:以前只见过linux from scratch与beyond linux from scratch，没想到连fpga都要from scratch了，转贴之。
看了这篇**，不禁有到安富利买板的冲动，不过895个美刀，贵，贵，贵。

http://www.us.design-reuse.com/articles/article16588.html

FPGA design from scratch

By Sven-Ake Andersson

I have been designing ASICs for more than 15 years. A few years ago I started to realize that there is another player in town and that is the FPGA circuit. With increasing NRE costs and with the long turn-around times, ASIC designs have become high-risk projects. At the same time FPGAs are getting bigger and faster and many companies have therefore decided to only use FPGAs. I also realized that I have to learn how to design using FPGAs, if I were to get any consulting jobs, especially here in Sweden. This is my story of how I hopefully will learn to use FPGAs in my future designs.

只看该作者 · 2007-9-5 11:56

Part 1
    * Introduction
    * Ordering the MicroBlaze development kit
    * Installing the Integrated Software Environment (ISE)
    * Running a board demo test

只看该作者 · 2007-9-5 11:57

Part 2
* Design object description

只看该作者 · 2007-9-5 11:57

Part 3

* Setting up the Integrated Software Environment (ISE) design software
* Running the Integrated Software Environment (ISE) design software

只看该作者 · 2007-9-5 11:58

Part 4

    * Adding Verilog source code
    * Generating memories using Coregen
    * Synthesizing the design
    * Simulating the design (Introduction)

只看该作者 · 2007-9-5 11:58

Part 5

* Setting up the simulation environment using Mongoose

只看该作者 · 2007-9-5 11:59

Part 6

    * The simulation process
    * Compiling macro libraries
    * Compiling the design
    * Compiling the testbench
    * Elaborating everything

只看该作者 · 2007-9-5 11:59

Part 7

* Testbench description

只看该作者 · 2007-9-5 12:00

Part 8

* Using HAL the HDL analysis and linting tool from Cadence

只看该作者 · 2007-9-5 12:00

Part 9

* Regression testing using Mongoose

只看该作者 · 2007-9-5 12:00

Part 10

* Synthesis using timing constraints (Introduction)

只看该作者 · 2007-9-5 12:01

Part 11

* The Field Programmable Gate Array (FPGA) description

只看该作者 · 2007-9-5 12:01

Part 12

* Adding synthesis constraints

只看该作者 · 2007-9-5 12:02

Part 13

* The MicroBlaze soft processor core
* Compiling simulation libraries using compedklib

只看该作者 · 2007-9-5 12:02

Part 14

    * Putting everything together
    * Installing ISE WebPack 9.1i
    * Installing EDK 9.1i

只看该作者 · 2007-9-5 12:03

Part 15

    * Xilinx Platform Studio XPS
    * Software Development Kit SDK
    * Create a new project in XPS
    * Generate a design report file

只看该作者 · 2007-9-5 12:03

Part 16

    * Create or import an user peripheral
    * The MHS file
    * XPS project files
    * Xilinx IP center

只看该作者 · 2007-9-5 12:03

Part 17

    * Adding the ETC IP
    * Generate the system netlist using platgen
    * What happend during the netlist generation
    * Generate simulation HDL files

只看该作者 · 2007-9-5 12:04

Part 18

    * Putting together a system simulation environment
    * The simulation database
    * The cds.lib file
    * Compiling the ETC IP
    * Compiling the block RAM
    * Compiling Verilog wrappers
    * Compiling VHDL wrappers
    * Elaborating the design
    * Warning messages

只看该作者 · 2007-9-5 12:05

Part 19

* Generating a Verilog testbench

[ZT]FPGA design from scratch

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