FPGA读写SRAM

只看该作者 · 2012-4-17 09:28

选用cypress的nv14b104na作为SRAM，通过FPGA读写，一直没有成功，想请高手帮忙分析一下原因：
EA<=SRAM_Addr;

process (Rst,Clk80m)

begin

if (Rst ='1') then

ECE<='1';

--CE,OE,WE均是低电平有效

EOE<='1';

EWE<='1';

Rd_Wr<='0';

SRAM_Addr<=(others=>'0');

SRAM_Data<=(others=>'0');

SRAM_Data1<=
"0000000000010001";

State<=(others=>'0');

elsif rising_edge(Clk80m) then

if(State="00000")then

if(Rd_Wr='1')then

--Rd_Wr=1代表读NVSRAM,0代表写NVSRAM

State<="00001";

else

State<="10000";

end if;

elsif(State="00001")then
--读NVSRAM

ECE<='0';

EOE<='0';

SRAM_Addr<="000000000000000010";

State<="00010";

elsif(State="00010")then

SRAM_Data1<=ED;

State<="00011";

elsif(State="00011")then

EOE<='1';

State<=(others=>'1');

elsif(State="10000")then
--写NVSRAM

SRAM_Addr<="000000000000000010";

SRAM_Data<="0000000010010001";

State<="10010";

EWE<='0';

elsif(State="10010")then

ED<=SRAM_Data;

State<="10011";

elsif(State="10011")then

EWE<='1';

                        State<="10111";

Rd_Wr<= not Rd_Wr;
                  elsif(State<="10111")then
                        ED<='Z';
                        State<=(others=>'0');
                  else

EWE<='1';

EOE<='1';

ECE<='1';

end if;

end if;

end process;

process (Rst,Clk100h)

begin

if (Rst ='1') then

flag<=(others=>'0');

elsif rising_edge(Clk100h) then

flag<=flag+1;

if(flag>SRAM_Data1)then

FPGA_WORK<=not FPGA_WORK;

flag<=(others=>'0');

end if;

end if;

end process;