同步下降沿检测

1万 · 2022-12-29 21:55

module cy4(

       input sig_a,

       input clk,

       input rstb,

       output sig_a_faledge

       );

reg sig_a_d1;

always @(posedge clk or negedge rstb)

  if(!rstb) sig_a_d1 <= 1'b0;

  else sig_a_d1 <= sig_a;

assign sig_a_faledge = !sig_a & sig_a_d1;



endmodule

测试脚本代码：

`timescale 1 ns/ 1 ps
module cy4_vlg_tst();

reg eachvec;

reg clk;
reg rstb;
reg sig_a;

wire sig_a_faledge;

cy4 i1 (
.clk(clk),
.rstb(rstb),
.sig_a(sig_a),
.sig_a_faledge(sig_a_faledge)
);

initial
begin
sig_a = 1;
clk = 0;
rstb = 0;

100;

rstb = 1;

100;

sig_a = 0;

100;

<span id="MathJax-Element-1-Frame" tabindex="0" data-mathml="stop;" role="presentation" style="box-sizing: border-box; border: 0px; font: inherit; vertical-align: baseline; position: relative;">stop;stop;display(“Running testbench”);
end
always #20 clk = ~clk ;
endmodule