#define SD_CLK_DIV_INIT ((uint16_t)0x0076) /* SD clock division in initilization phase */
#define SD_CLK_DIV_TRANS ((uint16_t)0x0076) /* SD clock division in transmission phase *///0x0002
470ZG频率降到和初始化一样了,还是偶尔上电出现FR_NO_FILESYSTEM,再重启又能挂载到。换450ZG就没事,同样的程序,同样的板子,搞不懂了。 |
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